* @param len the length of the cache line to be flushed
* @return none
*/
-void xhci_flush_cache(uint32_t addr, u32 len)
+void xhci_flush_cache(uintptr_t addr, u32 len)
{
BUG_ON((void *)addr == NULL || len == 0);
* @param len the length of the cache line to be invalidated
* @return none
*/
-void xhci_inval_cache(uint32_t addr, u32 len)
+void xhci_inval_cache(uintptr_t addr, u32 len)
{
BUG_ON((void *)addr == NULL || len == 0);
BUG_ON(!ptr);
memset(ptr, '\0', size);
- xhci_flush_cache((uint32_t)ptr, size);
+ xhci_flush_cache((uintptr_t)ptr, size);
return ptr;
}
/* Point to output device context in dcbaa. */
ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
- xhci_flush_cache((uint32_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
- sizeof(__le64));
+ xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
+ sizeof(__le64));
return 0;
}
entry->rsvd = 0;
seg = seg->next;
}
- xhci_flush_cache((uint32_t)ctrl->erst.entries,
- ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
+ xhci_flush_cache((uintptr_t)ctrl->erst.entries,
+ ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
deq = (unsigned long)ctrl->event_ring->dequeue;
/* this is the event ring segment table pointer */
val_64 = xhci_readq(&ctrl->ir_set->erst_base);
val_64 &= ERST_PTR_MASK;
- val_64 |= ((u32)(ctrl->erst.entries) & ~ERST_PTR_MASK);
+ val_64 |= ((uintptr_t)(ctrl->erst.entries) & ~ERST_PTR_MASK);
xhci_writeq(&ctrl->ir_set->erst_base, val_64);
/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
- xhci_flush_cache((uint32_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
- xhci_flush_cache((uint32_t)slot_ctx, sizeof(struct xhci_slot_ctx));
+ xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
+ xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));
}