ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c

[karo-tx-uboot.git] / drivers / usb / phy / omap_usb_phy.c

diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 52a3664b99ba43d862e57552c1d1db663a09c031..63d930168112fb4a692ed4f80578695996c0e90e 100644 (file)
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -131,17 +131,6 @@ static void omap_enable_usb3_phy(struct omap_xhci *omap)
 {
        u32     val;
 
-       /* Setting OCP2SCP1 register */
-       setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
-                    OCP2SCP1_CLKCTRL_MODULEMODE_HW);
-
-       /* Turn on 32K AON clk */
-       setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
-                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-       /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
-       writel(0x0, (*prcm)->cm_l3init_clkstctrl);
-
        val = (USBOTGSS_DMADISABLE |
                        USBOTGSS_STANDBYMODE_SMRT_WKUP |
                        USBOTGSS_IDLEMODE_NOIDLE);
@@ -169,11 +158,6 @@ static void omap_enable_usb3_phy(struct omap_xhci *omap)
        writel(val, &omap->otg_wrapper->irqstatus_1);
        val = readl(&omap->otg_wrapper->irqstatus_0);
        writel(val, &omap->otg_wrapper->irqstatus_0);
-
-       /* Enable the USB OTG Super speed clocks */
-       val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
-       setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
-
 };
 #endif /* CONFIG_OMAP_USB3PHY1_HOST */