hrtimer: fixup the HRTIMER_CB_IRQSAFE_NO_SOFTIRQ fallback

[mv-sheeva.git] / include / asm-mips / cpu-info.h

diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360bb5712e9c5b4607ae7d1e1152d66..ed5c02c6afbbafa98420565c8f7a88c74bbe2e27 100644 (file)
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,7 @@ struct cpuinfo_mips {
        struct cache_desc       dcache; /* Primary D or combined I/D cache */
        struct cache_desc       scache; /* Secondary cache */
        struct cache_desc       tcache; /* Tertiary/split secondary cache */
+       int                     srsets; /* Shadow register sets */
 #if defined(CONFIG_MIPS_MT_SMTC)
        /*
         * In the MIPS MT "SMTC" model, each TC is considered