[MIPS] Clean up asm-mips/mach-generic/spaces.h

[karo-tx-linux.git] / include / asm-mips / cpu.h

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 818b9a97e214280c0c6a93af52699028e32a95bb..2924069075e0a3b3a3342868d593de128ed880cc 100644 (file)
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,6 +51,7 @@
 #define PRID_IMP_R4300         0x0b00
 #define PRID_IMP_VR41XX                0x0c00
 #define PRID_IMP_R12000                0x0e00
+#define PRID_IMP_R14000                0x0f00
 #define PRID_IMP_R8000         0x1000
 #define PRID_IMP_PR4450                0x1200
 #define PRID_IMP_R4600         0x2000
@@ -87,6 +88,7 @@
 #define PRID_IMP_24K           0x9300
 #define PRID_IMP_34K           0x9500
 #define PRID_IMP_24KE          0x9600
+#define PRID_IMP_74K           0x9700
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -122,6 +124,17 @@
 #define PRID_REV_VR4181A       0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130                0x0080
 
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)                                   \
+       ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)                           \
+       ((ver) << 5 | (rev) << 2 | (patch))
+
 /*
  * FPU implementation/revision register (CP1 control register 0).
  *
@@ -196,7 +209,9 @@
 #define CPU_34K                        60
 #define CPU_PR4450             61
 #define CPU_SB1A               62
-#define CPU_LAST               62
+#define CPU_74K                        63
+#define CPU_R14000             64
+#define CPU_LAST               64
 
 /*
  * ISA Level encodings
@@ -238,7 +253,7 @@
 #define MIPS_CPU_EJTAG         0x00008000 /* EJTAG exception */
 #define MIPS_CPU_NOFPUEX       0x00010000 /* no FPU exception */
 #define MIPS_CPU_LLSC          0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_INCLUSIVE_CACHES      0x00040000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH      0x00080000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT          0x00100000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC          0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */