Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

[mv-sheeva.git] / include / asm-sh / system.h

diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index b1e42e7f998b5639a41f57281a35d1d89c7c1ab6..82f3e229e62135c2e944e1fbbe5e316744e2c4c1 100644 (file)
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -7,7 +7,9 @@
  */
 
 #include <linux/irqflags.h>
+#include <linux/compiler.h>
 #include <asm/types.h>
+#include <asm/ptrace.h>
 
 /*
  *     switch_to() should switch tasks to task nr n, first
@@ -80,16 +82,6 @@ static inline void sched_cacheflush(void)
 }
 #endif
 
-static inline unsigned long tas(volatile int *m)
-{
-       unsigned long retval;
-
-       __asm__ __volatile__ ("tas.b    @%1\n\t"
-                             "movt     %0"
-                             : "=r" (retval): "r" (m): "t", "memory");
-       return retval;
-}
-
 /*
  * A brief note on ctrl_barrier(), the control register write barrier.
  *
@@ -254,6 +246,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
                                    (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+
 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 
 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
@@ -261,6 +255,15 @@ static inline void *set_exception_table_evt(unsigned int evt, void *handler)
        return set_exception_table_vec(evt >> 5, handler);
 }
 
+/*
+ * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
+ */
+#ifdef CONFIG_CPU_SH2A
+extern unsigned int instruction_size(unsigned int insn);
+#else
+#define instruction_size(insn) (2)
+#endif
+
 /* XXX
  * disable hlt during certain critical i/o operations
  */