#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
+#include <linux/msi.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
#include <asm/iommu.h>
/* The abstraction used here is that there are PCI controllers,
/* Opaque 32-bit system bus Port ID. */
u32 portid;
+ /* Opaque 32-bit handle used for hypervisor calls. */
+ u32 devhandle;
+
/* Chipset version information. */
int chip_type;
#define PBM_CHIP_TYPE_SABRE 1
int chip_revision;
/* Name used for top-level resources. */
- char name[64];
+ char *name;
/* OBP specific information. */
- int prom_node;
- char prom_name[64];
- struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX];
+ struct device_node *prom_node;
+ struct linux_prom_pci_ranges *pbm_ranges;
int num_pbm_ranges;
- struct linux_prom_pci_intmap pbm_intmap[PROM_PCIIMAP_MAX];
+ struct linux_prom_pci_intmap *pbm_intmap;
int num_pbm_intmap;
- struct linux_prom_pci_intmask pbm_intmask;
+ struct linux_prom_pci_intmask *pbm_intmask;
u64 ino_bitmap;
/* PBM I/O and Memory space resources. */
int is_66mhz_capable;
int all_devs_66mhz;
+#ifdef CONFIG_PCI_MSI
+ /* MSI info. */
+ u32 msiq_num;
+ u32 msiq_ent_count;
+ u32 msiq_first;
+ u32 msiq_first_devino;
+ u32 msi_num;
+ u32 msi_first;
+ u32 msi_data_mask;
+ u32 msix_data_width;
+ u64 msi32_start;
+ u64 msi64_start;
+ u32 msi32_len;
+ u32 msi64_len;
+ void *msi_queues;
+ unsigned long *msi_bitmap;
+#endif /* !(CONFIG_PCI_MSI) */
+
/* This PBM's streaming buffer. */
struct pci_strbuf stc;
/* Operations which are controller specific. */
void (*scan_bus)(struct pci_controller_info *);
- unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
void (*base_address_update)(struct pci_dev *, int);
void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
+#ifdef CONFIG_PCI_MSI
+ int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
+ struct msi_desc *entry);
+ void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
+#endif
+
/* Now things for the actual PCI bus probes. */
struct pci_ops *pci_ops;
unsigned int pci_first_busno;
unsigned int pci_last_busno;
-
- void *starfire_cookie;
};
/* PCI devices which are not bridges have this placed in their pci_dev
*/
struct pcidev_cookie {
struct pci_pbm_info *pbm;
- char prom_name[64];
- int prom_node;
+ struct device_node *prom_node;
+ struct of_device *op;
struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
int num_prom_regs;
struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
int num_prom_assignments;
+#ifdef CONFIG_PCI_MSI
+ unsigned int msi_num;
+#endif
};
/* Currently these are the same across all PCI controllers