x86: don't set IO APIC features if IO APIC is not enabled

[mv-sheeva.git] / include / asm-x86 / kvm_host.h

diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 44b89259f6c497052ceab007e7c6d997dd5e5f18..68ee390b2844024eac9beb1444790870cc628483 100644 (file)
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -22,15 +22,16 @@
 
 #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
 #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
-#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS|0xFFFFFF0000000000ULL)
+#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |   \
+                                 0xFFFFFF0000000000ULL)
 
-#define KVM_GUEST_CR0_MASK \
+#define KVM_GUEST_CR0_MASK                                \
        (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \
         | X86_CR0_NW | X86_CR0_CD)
-#define KVM_VM_CR0_ALWAYS_ON \
+#define KVM_VM_CR0_ALWAYS_ON                                           \
        (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \
         | X86_CR0_MP)
-#define KVM_GUEST_CR4_MASK \
+#define KVM_GUEST_CR4_MASK                                             \
        (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
@@ -133,12 +134,12 @@ struct kvm_pte_chain {
 union kvm_mmu_page_role {
        unsigned word;
        struct {
-               unsigned glevels : 4;
-               unsigned level : 4;
-               unsigned quadrant : 2;
-               unsigned pad_for_nice_hex_output : 6;
-               unsigned metaphysical : 1;
-               unsigned access : 3;
+               unsigned glevels:4;
+               unsigned level:4;
+               unsigned quadrant:2;
+               unsigned pad_for_nice_hex_output:6;
+               unsigned metaphysical:1;
+               unsigned access:3;
        };
 };
 
@@ -224,6 +225,11 @@ struct kvm_vcpu_arch {
        int   last_pt_write_count;
        u64  *last_pte_updated;
 
+       struct {
+               gfn_t gfn;          /* presumed gfn during guest pte update */
+               struct page *page;  /* page corresponding to that gfn */
+       } update_pte;
+
        struct i387_fxsave_struct host_fx_image;
        struct i387_fxsave_struct guest_fx_image;
 
@@ -410,8 +416,10 @@ enum emulation_result {
        EMULATE_FAIL,         /* can't emulate this instruction */
 };
 
+#define EMULTYPE_NO_DECODE         (1 << 0)
+#define EMULTYPE_TRAP_UD           (1 << 1)
 int emulate_instruction(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                       unsigned long cr2, u16 error_code, int no_decode);
+                       unsigned long cr2, u16 error_code, int emulation_type);
 void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context);
 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
 void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
@@ -599,6 +607,7 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
 #define TSS_BASE_SIZE 0x68
 #define TSS_IOPB_SIZE (65536 / 8)
 #define TSS_REDIRECTION_SIZE (256 / 8)
-#define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
+#define RMODE_TSS_SIZE                                                 \
+       (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
 
 #endif