Add auto-update code for TRAB board using USB memory sticks

[karo-tx-uboot.git] / include / configs / IceCube.h

diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 2a455f8922967ee244db233e6f20159f8c84495d..204f332644fa7cc63ddbc40540d85523e7d994c2 100644 (file)
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,7 +37,7 @@
 #define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM          0x02    /* Software reboot           */
 
-#define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU */
+#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
 #endif
@@ -49,10 +49,43 @@
 #define CONFIG_BAUDRATE                115200  /* ... at 115200 bps */
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
 
+
+#ifdef CONFIG_MPC5200  /* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI             1
+#define CONFIG_PCI_PNP         1
+#define CONFIG_PCI_SCAN_SHOW   1
+
+#define CONFIG_PCI_MEM_BUS     0x40000000
+#define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE    0x10000000
+
+#define CONFIG_PCI_IO_BUS      0x50000000
+#define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE     0x01000000
+
+#define CONFIG_NET_MULTI       1
+#define CONFIG_EEPRO100                1
+#define CFG_RX_ETH_BUFFER      8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X         1
+
+#define ADD_PCI_CMD            CFG_CMD_PCI
+
+#else  /* MPC5100 */
+
+#define ADD_PCI_CMD            0  /* no CFG_CMD_PCI */
+
+#endif
+
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS                CONFIG_CMD_DFL
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | ADD_PCI_CMD | \
+                                CFG_CMD_I2C | CFG_CMD_EEPROM)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -64,42 +97,72 @@
 #define CONFIG_BOOTCOMMAND     "bootm 100000"  /* autoboot command */
 #define CONFIG_BOOTARGS                "root=/dev/ram rw"
 
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133                /* define for 133MHz speed */
+#endif
 /*
  * I2C configuration
  */
+#define CONFIG_HARD_I2C                1       /* I2C with hardware support */
+#define CFG_I2C_MODULE         1       /* If defined then I2C module #2 is used
+                                        * otherwise I2C module #1 is used */
+#ifdef CONFIG_MPC5200
+#define CFG_I2C_SPEED          0x3D    /* 86KHz given 133MHz IPBI */
+#else
+#define CFG_I2C_SPEED          0x35    /* 86KHz given 33MHz IPBI */
+#endif
+#define CFG_I2C_SLAVE          0x7F
 
 /*
- * Flash configuration
+ * EEPROM configuration
  */
-#define CFG_FLASH_BASE         0xff800000
-#define CFG_FLASH_SIZE         0x00800000
+#define CFG_I2C_EEPROM_ADDR            0x50    /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN                1
+#define CFG_EEPROM_PAGE_WRITE_BITS     3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 35
 
 /*
- * Flash organization
+ * Flash configuration
  */
+#define CFG_FLASH_16M          1
+
+#if !defined(CFG_FLASH_16M) /* 8Mb chips support only */
+#define CFG_FLASH_BASE         0xff800000
+#define CFG_FLASH_SIZE         0x00800000
 #define CFG_MAX_FLASH_BANKS    1       /* max num of memory banks      */
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x740000)
+#else
+#define CFG_FLASH_BASE         0xff000000
+#define CFG_FLASH_SIZE         0x01000000
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x740000 + 0x800000)
+#define CFG_MAX_FLASH_BANKS    2       /* max num of memory banks      */
+#endif
+
 #define CFG_MAX_FLASH_SECT     128     /* max num of sects on one chip */
 
 #define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
 
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
+#undef CONFIG_FLASH_16BIT      /* Flash is 8-bit */
 
 
 /*
  * Environment settings
  */
-#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_IN_FLASH    1
 #define CFG_ENV_SIZE           0x10000
-#define CFG_ENV_ADDR        (CFG_FLASH_BASE + 0x740000)
-#define CFG_ENV_SECT_SIZE   0x10000
-
+#define CFG_ENV_SECT_SIZE      0x10000
+#define CONFIG_ENV_OVERWRITE   1
 
 /*
  * Memory map
  */
 #define CFG_MBAR               0xf0000000
 #define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
 
 /* Use SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR      MPC5XXX_SRAM
@@ -112,7 +175,7 @@
 
 #define CFG_MONITOR_BASE    TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT 1
+#   define CFG_RAMBOOT         1
 #endif
 
 #define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor   */
@@ -123,6 +186,7 @@
  * Ethernet configuration
  */
 #define CONFIG_MPC5XXX_FEC     1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
 
 /*
  * GPIO configuration
@@ -153,8 +217,8 @@
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT          0
-#define CFG_HID0_FINAL         0
+#define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL         HID0_ICE
 
 #define CFG_BOOTCS_START       CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE