#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CONFIG_NS8382X 1
#define ADD_PCI_CMD CFG_CMD_PCI
/*
* Supported commands
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
+ CFG_CMD_I2C | CFG_CMD_EEPROM)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#endif
/*
* I2C configuration
*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
/*
- * Flash configuration
+ * EEPROM configuration
*/
-#define CFG_FLASH_BASE 0xff800000
-#define CFG_FLASH_SIZE 0x00800000
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
/*
- * Flash organization
+ * Flash configuration
*/
+#define CFG_FLASH_16M 1
+
+#if !defined(CFG_FLASH_16M) /* 8Mb chips support only */
+#define CFG_FLASH_BASE 0xff800000
+#define CFG_FLASH_SIZE 0x00800000
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
+#else
+#define CFG_FLASH_BASE 0xff000000
+#define CFG_FLASH_SIZE 0x01000000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000 + 0x800000)
+#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
+#endif
+
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
#define CFG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OVERWRITE 1
*/
#define CFG_MBAR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
* Ethernet configuration
*/
#define CONFIG_MPC5XXX_FEC 1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
/*
* GPIO configuration
*/
-#define CFG_GPS_PORT_CONFIG 0x00000004
+#define CFG_GPS_PORT_CONFIG 0x10000004
/*
* Miscellaneous configurable options
/*
* Various low-level settings
*/
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
+#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE