* Patch by Dave Ellis, 22 May 2003:

[karo-tx-uboot.git] / include / configs / MPC8260ADS.h

diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 14ad3139445c210b077446b7f10d99ccb86b5777..1849bcc1ec80f9dea51a011cba0b16dae9072ab6 100644 (file)
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -99,12 +99,22 @@
 #define CFG_I2C_SPEED          400000  /* I2C speed and slave address  */
 #define CFG_I2C_SLAVE          0x7F
 
+#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
+#define CONFIG_SPD_ADDR         0x50
+#endif
+
+#ifndef CONFIG_SDRAM_PBI
+#define CONFIG_SDRAM_PBI        1 /* By default, use page-based interleaving */
+#endif
 
+#ifndef CONFIG_8260_CLKIN
 #define CONFIG_8260_CLKIN      66666666        /* in Hz */
+#endif
 #define CONFIG_BAUDRATE                115200
 
 #define CONFIG_COMMANDS                (CFG_CMD_ALL & ~( \
                                 CFG_CMD_BEDBUG | \
+                                CFG_CMD_BMP    | \
                                 CFG_CMD_BSP    | \
                                 CFG_CMD_DATE   | \
                                 CFG_CMD_DOC    | \
@@ -112,10 +122,12 @@
                                 CFG_CMD_EEPROM | \
                                 CFG_CMD_ELF    | \
                                 CFG_CMD_FDC    | \
+                                CFG_CMD_FDOS   | \
                                 CFG_CMD_HWFLOW | \
                                 CFG_CMD_IDE    | \
                                 CFG_CMD_JFFS2  | \
                                 CFG_CMD_KGDB   | \
+                                CFG_CMD_NAND   | \
                                 CFG_CMD_MII    | \
                                 CFG_CMD_PCI    | \
                                 CFG_CMD_PCMCIA | \
@@ -179,7 +191,7 @@
 /* this is stuff came out of the Motorola docs */
 #define CFG_DEFAULT_IMMR       0x0F010000
 
-#define CFG_IMMR               0x04700000
+#define CFG_IMMR               0xF0000000
 #define CFG_BCSR               0x04500000
 #define CFG_SDRAM_BASE         0x00000000
 #define CFG_LSDRAM_BASE                0x04000000