net: fec_mxc: move CONFIG_FEC_MXC_PHYADDR from Kconfig to include/configs/*.h

[karo-tx-uboot.git] / include / configs / maxbcm.h

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 27ea71fe616f4c169c490eed49f5a014dee0aa0e..3530a2621389c9df30ed8aecffbc6b07dcfdc764 100644 (file)
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -15,14 +15,18 @@
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
-#define        CONFIG_SYS_TEXT_BASE    0x04000000
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define        CONFIG_SYS_TEXT_BASE    0x00800000
 #define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 
 /*
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH            /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_I2C
@@ -44,7 +48,6 @@
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_3
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
 
 /* Environment in SPI NOR flash */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -53,7 +56,7 @@
 #define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64KiB sectors */
 
 #define CONFIG_PHY_MARVELL             /* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR   0x0
+#define CONFIG_PHY_ADDR                        { 0x0, 0x1, 0x2, 0x3 }
 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 #define CONFIG_RESET_PHY_R
@@ -100,7 +103,6 @@
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT            "arch/arm/mach-mvebu/u-boot-spl.lds"
 
 /* SPL related SPI defines */
 #define CONFIG_SPL_SPI_SUPPORT
@@ -111,7 +113,7 @@
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_DDR_FIXED_SIZE          (1 << 20)       /* 1GiB */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */