/*
* Malloc pool need to host env + 128 Kb reserve for other allocations.
*/
-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
+#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_MONITOR_BASE 0x10000000
#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
-#define CFG_ENV_SIZE 0x20000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
+#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
#define CFG_CS5U_VAL 0x00008400
#define CFG_CS5L_VAL 0x00000D03
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x16000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
-/* #define CONFIG_DM9000_USE_8BIT */
-#define CONFIG_DM9000_USE_16BIT
-/* #define CONFIG_DM9000_USE_32BIT */
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
f_ref=16,777MHz