#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
+#define CONFIG_CRC32_VERIFY
+
#define CONFIG_FIT
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
/* Enable multiple SPI NOR flash manufacturers */
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=ff705000.spi"
+#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
#endif
-#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
+#if CONFIG_IS_ENABLED(OF_CONTROL) /* DW SPI is controlled via DT */
#define CONFIG_DESIGNWARE_SPI
#define CONFIG_CMD_SPI
#endif
#define CONFIG_SYS_MALLOC_SIMPLE
#endif
-#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
-#define CONFIG_CRC32_VERIFY
-
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
-#endif
-
#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */