usb: USB download gadget and functions config options coherent naming

[karo-tx-uboot.git] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 38d9e8a752cb25280aa13e9c546a2d3491870a84..e8473b872adf82438e82bf6ce6ae94cf8c59b1b2 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -3,14 +3,16 @@
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
 
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_SYS_THUMB_BUILD
 
-
 /*
  * High level configuration
  */
@@ -36,12 +38,13 @@
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR                                        \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -  \
        GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE           0x08000040
 #else
 #define CONFIG_SYS_TEXT_BASE           0x01000040
@@ -78,7 +81,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED                30000000
-#define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_BAR
 /*
@@ -93,8 +95,7 @@
 /*
  * Ethernet on SoC (EMAC)
  */
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_NET_MULTI
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
@@ -119,6 +120,7 @@
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TIMER_RATE          2400000
 #else
 #define CONFIG_SYS_TIMER_RATE          25000000
@@ -142,6 +144,10 @@
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL    3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL    0
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
@@ -180,7 +186,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #ifdef CONFIG_OF_CONTROL       /* QSPI is controlled via DT */
 #define CONFIG_CADENCE_QSPI
 /* Enable multiple SPI NOR flash manufacturers */
-#define CONFIG_SPI_FLASH               /* SPI flash subsystem */
 #define CONFIG_SPI_FLASH_STMICRO       /* Micron/Numonyx flash */
 #define CONFIG_SPI_FLASH_SPANSION      /* Spansion flash */
 #define CONFIG_SPI_FLASH_MTD
@@ -205,6 +210,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4
 #define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK         1000000
 #else
 #define CONFIG_SYS_NS16550_CLK         100000000
@@ -237,10 +243,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_USB_GADGET_VBUS_DRAW    2
 
 /* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_DFU_FUNCTION
+#define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
 #define DFU_DEFAULT_POLL_TIMEOUT       300
@@ -281,19 +287,26 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START    CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE     (5 * 1024)
+#define CONFIG_SPL_MAX_SIZE            (64 * 1024)
 
 #define CHUNKSZ_CRC32                  (1 * 1024)      /* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY
 
 /* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT    "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT    "arch/arm/mach-socfpga/u-boot-spl.lds"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
+
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS
 #endif
 
+#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */