ppc, 8321: cleanup tuxa1, tuda1 and suvd3 support

[karo-tx-uboot.git] / include / configs / tuda1.h

diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
index 7ada9d5ec2f528d0a9673b19f5b66e46502facdd..1c0b3e0034227e15f450c8b0f375a10e02695ca6 100644 (file)
--- a/include/configs/tuda1.h
+++ b/include/configs/tuda1.h
@@ -26,110 +26,20 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_QE              /* Has QE */
-#define CONFIG_MPC832x         /* MPC832x CPU specific */
 #define CONFIG_TUDA1           /* TUDA1 board specific */
 #define CONFIG_HOSTNAME                tuda1
 #define CONFIG_KM_BOARD_NAME   "tuda1"
 
 #define        CONFIG_SYS_TEXT_BASE    0xF0000000
-#define CONFIG_KM_DEF_NETDEV   \
-       "netdev=eth0\0"
 
-#define CONFIG_KM_DEF_ROOTPATH         \
-       "rootpath=/opt/eldk/ppc_8xx\0"
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
 
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDR_CS0_BNDS                0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-                                        SDRAM_CFG_32_BE | \
-                                        SDRAM_CFG_2T_EN | \
-                                        SDRAM_CFG_SREN)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL                (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL        ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-                                (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN | CSCONFIG_AP | \
-                                        CSCONFIG_ODT_WR_CFG | \
-                                        CSCONFIG_ROW_BIT_13 | \
-                                        CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE    0x47860252
-#define CONFIG_SYS_DDR_MODE2   0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0        ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-                                (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-                                (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-                                (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-                                (0 << TIMING_CFG0_WWT_SHIFT) | \
-                                (0 << TIMING_CFG0_RRT_SHIFT) | \
-                                (0 << TIMING_CFG0_WRT_SHIFT) | \
-                                (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1        ((TIMING_CFG1_CASLAT_50) | \
-                                (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-                                (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-                                (2 << TIMING_CFG1_WRREC_SHIFT) | \
-                                (6 << TIMING_CFG1_REFREC_SHIFT) | \
-                                (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-                                (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-                                (2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2        ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-                                (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-                                (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-                                (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-                                (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-                                (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-                                (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3        0x00000000
-
-
-#define CONFIG_SYS_PIGGY_BASE  0xE8000000
-#define        CONFIG_SYS_PIGGY_SIZE   128
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */
 #define        CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
 
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
 /*
  * Local Bus Configuration & Clock Setup
  */
@@ -209,22 +119,6 @@
                                 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
 
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CFG_IBAT6L     (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U     (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L     CFG_IBAT6L
-#define CFG_DBAT6U     CFG_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L     (CFG_PCI1_MMIO_PHYS | \
-                        BATL_PP_10 | \
-                        BATL_CACHEINHIBIT | \
-                        BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U     (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L     CFG_IBAT7L
-#define CFG_DBAT7U     CFG_IBAT7U
-#else /* CONFIG_PCI */
-
 /* PINC3:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L      (CONFIG_SYS_APP2_BASE | \
                                 BATL_PP_10 | \
@@ -243,6 +137,5 @@
 #define CONFIG_SYS_IBAT7U      (0)
 #define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
 
 #endif /* __CONFIG_H */