clk: arm: snapdragon: add () around macro args and fixup indentation

[karo-tx-uboot.git] / include / fsl_ddr_sdram.h

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 3699c0408a11aeeee2354b471e5a63174f12d924..36bd9d7c934a7a299a147a5c0c0d29bb15d8aa60 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -123,6 +123,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 
 #define SDRAM_CFG2_FRC_SR              0x80000000
 #define SDRAM_CFG2_D_INIT              0x00000010
+#define SDRAM_CFG2_AP_EN               0x00000020
 #define SDRAM_CFG2_ODT_CFG_MASK                0x00600000
 #define SDRAM_CFG2_ODT_NEVER           0
 #define SDRAM_CFG2_ODT_ONLY_WRITE      1
@@ -145,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define WR_DATA_DELAY_SHIFT    10
 #endif
 
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS    0x07000000
+#define DDR_EOR_WD_REOD_DIS    0x00100000
+
 /* DDR_MD_CNTL */
 #define MD_CNTL_MD_EN          0x80000000
 #define MD_CNTL_CS_SEL_CS0     0x00000000
@@ -177,6 +182,21 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
 #define DDR_CDR2_VREF_RANGE_2  0x00000040
 
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED   (1 << 8)  /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK    0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK    0x2 /* for DDR4-2400 */
+
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS  (1 << 10) /* Transmit Bit Deskew Disable */
+
+
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
 #ifdef CONFIG_SYS_FSL_DDR3L
@@ -279,7 +299,7 @@ typedef struct fsl_ddr_cfg_regs_s {
        unsigned int ddr_cdr2;
        unsigned int err_disable;
        unsigned int err_int_en;
-       unsigned int debug[32];
+       unsigned int debug[64];
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
@@ -343,7 +363,7 @@ typedef struct memctl_options_s {
        /* mirrior DIMMs for DDR3 */
        unsigned int mirrored_dimm;
        unsigned int quad_rank_present;
-       unsigned int ap_en;     /* address parity enable for RDIMM */
+       unsigned int ap_en;     /* address parity enable for RDIMM/DDR4-UDIMM */
        unsigned int x4_en;     /* enable x4 devices */
 
        /* Global Timing Parameters */