*
* Copyright 2014 Freescale Semiconductor, Inc.
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_SEC_H
/* RNG4 TRNG test registers */
struct rng4tst {
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
+ both entropy shifter and
+ statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
+ entropy shifter and
+ statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+ entropy shifter, raw data
+ in statistical checker */
+#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
u32 rtmctl; /* misc. control register */
u32 rtscmisc; /* statistical check misc. register */
u32 rtpkrrng; /* poker range register */
-#define RTSDCTL_ENT_DLY_MIN 1200
+#define RTSDCTL_ENT_DLY_MIN 3200
#define RTSDCTL_ENT_DLY_MAX 12800
union {
u32 rtpkrmax; /* PRGM=1: poker max. limit register */
#define CONFIG_JRSTARTR_JR0 0x00000001
struct jr_regs {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 irba_l;
u32 irba_h;
#else
u32 irsa;
u32 rsvd3;
u32 irja;
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 orba_l;
u32 orba_h;
#else
* related information
*/
struct sg_entry {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
#define SG_ENTRY_OFFSET_SHIFT 0
};
-#ifdef CONFIG_SOC_MX6
+#ifdef CONFIG_ARCH_MX6
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO (3 << 6)