Merge remote-tracking branch 'l2-mtd/master'

[karo-tx-linux.git] / include / linux / bcma / bcma_driver_chipcommon.h

diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index db51a6ffb7d6839ba1ffd08ffd072faed79031dc..700d0c6f7480e46f972a7f30756cbb3320f3dd6c 100644 (file)
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -217,6 +217,11 @@
 #define         BCMA_CC_CLKDIV_JTAG_SHIFT      8
 #define         BCMA_CC_CLKDIV_UART            0x000000FF
 #define BCMA_CC_CAP_EXT                        0x00AC          /* Capabilities */
+#define  BCMA_CC_CAP_EXT_SECI_PRESENT  0x00000001
+#define  BCMA_CC_CAP_EXT_GSIO_PRESENT  0x00000002
+#define  BCMA_CC_CAP_EXT_GCI_PRESENT   0x00000004
+#define  BCMA_CC_CAP_EXT_SECI_PUART_PRESENT            0x00000008    /* UART present */
+#define  BCMA_CC_CAP_EXT_AOB_PRESENT   0x00000040
 #define BCMA_CC_PLLONDELAY             0x00B0          /* Rev >= 4 only */
 #define BCMA_CC_FREFSELDELAY           0x00B4          /* Rev >= 4 only */
 #define BCMA_CC_SLOWCLKCTL             0x00B8          /* 6 <= Rev <= 9 only */
@@ -351,12 +356,12 @@
 #define BCMA_CC_PMU_RES_REQTS          0x0640 /* PMU res req timer sel */
 #define BCMA_CC_PMU_RES_REQT           0x0644 /* PMU res req timer */
 #define BCMA_CC_PMU_RES_REQM           0x0648 /* PMU res req mask */
-#define BCMA_CC_CHIPCTL_ADDR           0x0650
-#define BCMA_CC_CHIPCTL_DATA           0x0654
-#define BCMA_CC_REGCTL_ADDR            0x0658
-#define BCMA_CC_REGCTL_DATA            0x065C
-#define BCMA_CC_PLLCTL_ADDR            0x0660
-#define BCMA_CC_PLLCTL_DATA            0x0664
+#define BCMA_CC_PMU_CHIPCTL_ADDR       0x0650
+#define BCMA_CC_PMU_CHIPCTL_DATA       0x0654
+#define BCMA_CC_PMU_REGCTL_ADDR                0x0658
+#define BCMA_CC_PMU_REGCTL_DATA                0x065C
+#define BCMA_CC_PMU_PLLCTL_ADDR                0x0660
+#define BCMA_CC_PMU_PLLCTL_DATA                0x0664
 #define BCMA_CC_PMU_STRAPOPT           0x0668 /* (corerev >= 28) */
 #define BCMA_CC_PMU_XTAL_FREQ          0x066C /* (pmurev >= 10) */
 #define  BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK     0x00001FFF
@@ -566,6 +571,7 @@
  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  */
 struct bcma_chipcommon_pmu {
+       struct bcma_device *core;       /* Can be separated core or just ChipCommon one */
        u8 rev;                 /* PMU revision */
        u32 crystalfreq;        /* The active crystal frequency (in kHz) */
 };
@@ -660,6 +666,19 @@ struct bcma_drv_cc_b {
 #define bcma_cc_maskset32(cc, offset, mask, set) \
        bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
 
+/* PMU registers access */
+#define bcma_pmu_read32(cc, offset) \
+       bcma_read32((cc)->pmu.core, offset)
+#define bcma_pmu_write32(cc, offset, val) \
+       bcma_write32((cc)->pmu.core, offset, val)
+
+#define bcma_pmu_mask32(cc, offset, mask) \
+       bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
+#define bcma_pmu_set32(cc, offset, set) \
+       bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
+#define bcma_pmu_maskset32(cc, offset, mask, set) \
+       bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
+
 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
 
 extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);