memcg, slab: do not destroy children caches if parent has aliases

[karo-tx-linux.git] / include / linux / clk-provider.h

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253b86036b5d897a7b8e741c0ea3f5e4fdf4..511917416fb003bd27ba5817fb6c8ee1af8cf498 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -29,8 +29,10 @@
 #define CLK_IS_BASIC           BIT(5) /* Basic clk, can't do a to_clk_foo() */
 #define CLK_GET_RATE_NOCACHE   BIT(6) /* do not use the cached clk rate */
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
 
 struct clk_hw;
+struct dentry;
 
 /**
  * struct clk_ops -  Callback operations for hardware clocks; these are to
@@ -108,6 +110,31 @@ struct clk_hw;
  *             which is likely helpful for most .set_rate implementation.
  *             Returns 0 on success, -EERROR otherwise.
  *
+ * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
+ *             is expressed in ppb (parts per billion). The parent accuracy is
+ *             an input parameter.
+ *             Returns the calculated accuracy.  Optional - if this op is not
+ *             set then clock accuracy will be initialized to parent accuracy
+ *             or 0 (perfect clock) if clock has no parent.
+ *
+ * @set_rate_and_parent: Change the rate and the parent of this clock. The
+ *             requested rate is specified by the second argument, which
+ *             should typically be the return of .round_rate call.  The
+ *             third argument gives the parent rate which is likely helpful
+ *             for most .set_rate_and_parent implementation. The fourth
+ *             argument gives the parent index. This callback is optional (and
+ *             unnecessary) for clocks with 0 or 1 parents as well as
+ *             for clocks that can tolerate switching the rate and the parent
+ *             separately via calls to .set_parent and .set_rate.
+ *             Returns 0 on success, -EERROR otherwise.
+ *
+ * @debug_init:        Set up type-specific debugfs entries for this clock.  This
+ *             is called once, after the debugfs directory entry for this
+ *             clock has been created.  The dentry pointer representing that
+ *             directory is provided as an argument.  Called with
+ *             prepare_lock held.  Returns 0 on success, -EERROR otherwise.
+ *
+ *
  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  * implementations to split any work between atomic (enable) and sleepable
  * (prepare) contexts.  If enabling a clock requires code that might sleep,
@@ -139,7 +166,13 @@ struct clk_ops {
        u8              (*get_parent)(struct clk_hw *hw);
        int             (*set_rate)(struct clk_hw *hw, unsigned long,
                                    unsigned long);
+       int             (*set_rate_and_parent)(struct clk_hw *hw,
+                                   unsigned long rate,
+                                   unsigned long parent_rate, u8 index);
+       unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
+                                          unsigned long parent_accuracy);
        void            (*init)(struct clk_hw *hw);
+       int             (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
 };
 
 /**
@@ -194,6 +227,7 @@ struct clk_hw {
 struct clk_fixed_rate {
        struct          clk_hw hw;
        unsigned long   fixed_rate;
+       unsigned long   fixed_accuracy;
        u8              flags;
 };
 
@@ -201,6 +235,9 @@ extern const struct clk_ops clk_fixed_rate_ops;
 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                unsigned long fixed_rate);
+struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
+               const char *name, const char *parent_name, unsigned long flags,
+               unsigned long fixed_rate, unsigned long fixed_accuracy);
 
 void of_fixed_clk_setup(struct device_node *np);
 
@@ -433,6 +470,7 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
+unsigned long __clk_get_accuracy(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
@@ -458,6 +496,8 @@ struct clk_onecell_data {
        unsigned int clk_num;
 };
 
+extern struct of_device_id __clk_of_table;
+
 #define CLK_OF_DECLARE(name, compat, fn)                       \
        static const struct of_device_id __clk_of_table_##name  \
                __used __section(__clk_of_table)                \
@@ -512,6 +552,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
  * for improved portability across platforms
  */
 
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+       return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+       iowrite32be(val, reg);
+}
+
+#else  /* platform dependent I/O accessors */
+
 static inline u32 clk_readl(u32 __iomem *reg)
 {
        return readl(reg);
@@ -522,5 +576,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
        writel(val, reg);
 }
 
+#endif /* platform dependent I/O accessors */
+
 #endif /* CONFIG_COMMON_CLK */
 #endif /* CLK_PROVIDER_H */