#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
-#define EXT_CSD_BOOT_BUS_WIDTH 177 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
-#define EXT_CSD_BOOT_INFO 228 /* RO, 1 bytes */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
-#define EXT_CSD_BOOT_BUS_WIDTH_MASK (0x1F)
-#define EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK (0x3 << 3)
-#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_NORMAL (0x0)
-#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_HIGH (0x1)
-#define EXT_CSD_BOOT_BUS_WIDTH_MODE_DDR (0x2)
-#define EXT_CSD_BOOT_BUS_WIDTH_RST_WIDTH (1 << 2)
-#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK (0x3)
-#define EXT_CSD_BOOT_BUS_WIDTH_1_SDR_4_DDR (0x0)
-#define EXT_CSD_BOOT_BUS_WIDTH_4_SDR_4_DDR (0x1)
-#define EXT_CSD_BOOT_BUS_WIDTH_8_SDR_8_DDR (0x2)
-
-#define EXT_CSD_BOOT_ACK_ENABLE (0x1 << 6)
-#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3)
-#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0)
-#define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3)
-#define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3)
-#define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3)
-
-#define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7)
-#define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0)
-#define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1)
-#define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2)
-
#define EXT_CSD_RST_N_EN_MASK 0x3
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */