Merge tag 'sound-fix2-3.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

[karo-tx-linux.git] / include / linux / sh_dma.h

diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index 4e83f3e034f3873d531580550a1940b4b49f6461..b7b43b82231e0ae7fed55cae10c302ba4a04c105 100644 (file)
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -33,13 +33,44 @@ struct sh_dmae_slave_config {
        char            mid_rid;
 };
 
+/**
+ * struct sh_dmae_channel - DMAC channel platform data
+ * @offset:            register offset within the main IOMEM resource
+ * @dmars:             channel DMARS register offset
+ * @chclr_offset:      channel CHCLR register offset
+ * @dmars_bit:         channel DMARS field offset within the register
+ * @chclr_bit:         bit position, to be set to reset the channel
+ */
 struct sh_dmae_channel {
        unsigned int    offset;
        unsigned int    dmars;
-       unsigned int    dmars_bit;
        unsigned int    chclr_offset;
+       unsigned char   dmars_bit;
+       unsigned char   chclr_bit;
 };
 
+/**
+ * struct sh_dmae_pdata - DMAC platform data
+ * @slave:             array of slaves
+ * @slave_num:         number of slaves in the above array
+ * @channel:           array of DMA channels
+ * @channel_num:       number of channels in the above array
+ * @ts_low_shift:      shift of the low part of the TS field
+ * @ts_low_mask:       low TS field mask
+ * @ts_high_shift:     additional shift of the high part of the TS field
+ * @ts_high_mask:      high TS field mask
+ * @ts_shift:          array of Transfer Size shifts, indexed by TS value
+ * @ts_shift_num:      number of shifts in the above array
+ * @dmaor_init:                DMAOR initialisation value
+ * @chcr_offset:       CHCR address offset
+ * @chcr_ie_bit:       CHCR Interrupt Enable bit
+ * @dmaor_is_32bit:    DMAOR is a 32-bit register
+ * @needs_tend_set:    the TEND register has to be set
+ * @no_dmars:          DMAC has no DMARS registers
+ * @chclr_present:     DMAC has one or several CHCLR registers
+ * @chclr_bitwise:     channel CHCLR registers are bitwise
+ * @slave_only:                DMAC cannot be used for MEMCPY
+ */
 struct sh_dmae_pdata {
        const struct sh_dmae_slave_config *slave;
        int slave_num;
@@ -59,42 +90,22 @@ struct sh_dmae_pdata {
        unsigned int needs_tend_set:1;
        unsigned int no_dmars:1;
        unsigned int chclr_present:1;
+       unsigned int chclr_bitwise:1;
        unsigned int slave_only:1;
 };
 
-/* DMA register */
-#define SAR    0x00
-#define DAR    0x04
-#define TCR    0x08
-#define CHCR   0x0C
-#define DMAOR  0x40
-
-#define TEND   0x18 /* USB-DMAC */
-
 /* DMAOR definitions */
 #define DMAOR_AE       0x00000004
 #define DMAOR_NMIF     0x00000002
 #define DMAOR_DME      0x00000001
 
 /* Definitions for the SuperH DMAC */
-#define REQ_L  0x00000000
-#define REQ_E  0x00080000
-#define RACK_H 0x00000000
-#define RACK_L 0x00040000
-#define ACK_R  0x00000000
-#define ACK_W  0x00020000
-#define ACK_H  0x00000000
-#define ACK_L  0x00010000
 #define DM_INC 0x00004000
 #define DM_DEC 0x00008000
 #define DM_FIX 0x0000c000
 #define SM_INC 0x00001000
 #define SM_DEC 0x00002000
 #define SM_FIX 0x00003000
-#define RS_IN  0x00000200
-#define RS_OUT 0x00000300
-#define TS_BLK 0x00000040
-#define TM_BUR 0x00000020
 #define CHCR_DE        0x00000001
 #define CHCR_TE        0x00000002
 #define CHCR_IE        0x00000004