#define DISPC_IRQ_WAKEUP (1 << 16)
#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
#define DISPC_IRQ_VSYNC2 (1 << 18)
+#define DISPC_IRQ_VID3_END_WIN (1 << 19)
+#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
+#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
+#define DISPC_IRQ_FRAMEDONETV (1 << 24)
+#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
struct omap_dss_device;
struct omap_overlay_manager;
enum omap_plane {
OMAP_DSS_GFX = 0,
OMAP_DSS_VIDEO1 = 1,
- OMAP_DSS_VIDEO2 = 2
+ OMAP_DSS_VIDEO2 = 2,
+ OMAP_DSS_VIDEO3 = 3,
};
enum omap_channel {
OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
+ OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
};
enum omap_overlay_manager_caps {
bool enabled;
u32 paddr;
- void __iomem *vaddr;
u32 p_uv_addr; /* for NV12 format */
u16 screen_width;
u16 width;
u16 out_height; /* if 0, out_height == height */
u8 global_alpha;
u8 pre_mult_alpha;
+ u8 zorder;
};
struct omap_overlay {
u32 trans_key;
bool trans_enabled;
- bool alpha_enabled;
+ bool partial_alpha_enabled;
bool cpr_enable;
struct omap_dss_cpr_coefs cpr_coefs;
} dispc;
struct {
+ /* regn is one greater than TRM's REGN value */
u16 regn;
u16 regm;
u16 regm_dispc;
} dsi;
struct {
+ /* regn is one greater than TRM's REGN value */
u16 regn;
u16 regm2;
} hdmi;
int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
u32 (*get_wss)(struct omap_dss_device *dssdev);
+
+ int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
+ bool (*detect)(struct omap_dss_device *dssdev);
};
int omap_dss_register_driver(struct omap_dss_driver *);