#include <common.h>
#include <asm/io.h>
-#include <asm/immap_83xx.h>
#include <asm/fsl_lbc.h>
#include <linux/mtd/nand.h>
static void nand_wait(void)
{
- lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
for (;;) {
uint32_t status = in_be32(®s->ltesr);
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
- lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
- uchar *buf = (uchar *)CFG_NAND_BASE;
- int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
- int block_shift = large ? 17 : 14;
- int block_size = 1 << block_shift;
- int page_size = large ? 2048 : 512;
- int bad_marker = large ? page_size + 0 : page_size + 5;
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
+ uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+ const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+ const int block_shift = large ? 17 : 14;
+ const int block_size = 1 << block_shift;
+ const int page_size = large ? 2048 : 512;
+ const int bad_marker = large ? page_size + 0 : page_size + 5;
int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
int pos = 0;
pos += page_size;
offs += page_size;
- } while (offs & (block_size - 1));
+ } while ((offs & (block_size - 1)) && (pos < uboot_size));
}
}
{
__attribute__((noreturn)) void (*uboot)(void);
- udelay(1000000);
-
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
- (uchar *)CFG_NAND_U_BOOT_DST);
+ nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
/*
* Jump to U-Boot image
*/
puts("transfering control\n");
- uboot = (void *)CFG_NAND_U_BOOT_START;
+ /*
+ * Clean d-cache and invalidate i-cache, to
+ * make sure that no stale data is executed.
+ */
+ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}