TX27 GP Fkt GPIO Pad IOMUXC SW_PAD SW_PAD strap
GPIO ALT ALT OFFSET CTRL MUX option
FEC_MDC PD9 5 0 GPIO3_5 FEC_MDC 0x1c8 0x3c0
-FEC_MDIO PD8 5 0 GPIO3_6 FEC_MDIO 0x1cc 0x3c4
+FEC_MDIO PD8 5 0 GPIO3_6 FEC_MDIO 0x1cc 0x3c4
FEC_RX_CLK PD14 - - NC REGOFF: 0
-FEC_RX_DV PD13 - - NC
+FEC_RX_DV PD13 - - NC
FEC_RXD0 PD12 5 0 GPIO3_10 FEC_RDATA0 0x1dc 0x3d4 MODE0: 1
FEC_RXD1 PD5 5 0 GPIO3_11 FEC_RDATA1 0x1e0 0x3d8 MODE1: 1
FEC_RXD2 PD6 - - NC PULLUP MODE2: 1
FEC_RXD3 PD7 - - NC INTSEL: 0
FEC_RX_ER PD4 5 5 GPIO4_10 D10 0x09c 0x294
-FEC_TX_CLK PD11 5 0 GPIO3_13 FEC_TX_CLK 0x1e8 0x3e0
+FEC_TX_CLK PD11 5 0 GPIO3_13 FEC_TX_CLK 0x1e8 0x3e0
FEC_TX_EN PF23 5 0 GPIO3_9 FEC_TX_EN 0x1d8 0x3d0
FEC_TXD0 PD0 5 0 GPIO3_7 FEC_TDATA0 0x1d0 0x3c8
FEC_TXD1 PD1 5 0 GPIO3_8 FEC_TDATA1 0x1d4 0x3cc
cyg_uint8 shift;
} tx25_fec_gpio_data[] = {
/* iomux, func, gpfn, gpgrp, gpshift */
- { 0x1c8, 0, 0x15, 3, 5, },
- { 0x1cc, 0, 0x15, 3, 6, },
- { 0x1dc, 0, 0x15, 3, 10, },
- { 0x1e0, 0, 0x15, 3, 11, },
- { 0x09c, 0x85, 5, 4, 10, },
- { 0x1e8, 0, 0x15, 3, 13, },
- { 0x1d8, 0, 0x15, 3, 9, },
- { 0x1d0, 0, 0x15, 3, 7, },
- { 0x1d4, 0, 0x15, 3, 8, },
- { 0x1e4, 0x80, 0x15, 3, 12, },
- { 0x024, 0x05, 0x05, 2, 5, }, /* RX_ER signal; make sure it's a GPIO _without_ SION! */
- { 0x094, 0x85, 5, 4, 8, },
- { 0x090, 5, 5, 4, 7, },
- { 0x098, 5, 5, 4, 9, },
+ { 0x1c8, 0, 0x15, 3, 5, },
+ { 0x1cc, 0, 0x15, 3, 6, },
+ { 0x1dc, 0, 0x15, 3, 10, },
+ { 0x1e0, 0, 0x15, 3, 11, },
+ { 0x09c, 0x85, 5, 4, 10, },
+ { 0x1e8, 0, 0x15, 3, 13, },
+ { 0x1d8, 0, 0x15, 3, 9, },
+ { 0x1d0, 0, 0x15, 3, 7, },
+ { 0x1d4, 0, 0x15, 3, 8, },
+ { 0x1e4, 0x80, 0x15, 3, 12, },
+ { 0x024, 0x05, 0x05, 2, 5, }, /* RX_ER signal; make sure it's a GPIO _without_ SION! */
+ { 0x094, 0x85, 5, 4, 8, },
+ { 0x090, 5, 5, 4, 7, },
+ { 0x098, 5, 5, 4, 9, },
};
static struct tx25_gpio_setup tx25_fec_strap_pins[] = {
- { 0x1dc, 0, 0x15, 3, 10, },
- { 0x1e0, 0, 0x15, 3, 11, },
- { 0x1e4, 0, 0x15, 3, 12, },
+ { 0x1dc, 0, 0x15, 3, 10, },
+ { 0x1e0, 0, 0x15, 3, 11, },
+ { 0x1e4, 0, 0x15, 3, 12, },
};
static inline void tx25_phy_power_off(void)
}
}
-ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
- tx25_fec_phy_init,
- mxc_fec_phy_reset,
- mxc_fec_phy_write,
- mxc_fec_phy_read);
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
+ tx25_fec_phy_init,
+ mxc_fec_phy_reset,
+ mxc_fec_phy_write,
+ mxc_fec_phy_read);
#define SOC_MAC_ADDR_LOCK_BIT 2
if (cyg_plf_redboot_esa_validate(addr)) {
diag_printf("Ethernet FEC MAC address from fuse bank: ");
diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa_data", addr2, CONFIG_ESA);
if (memcmp(addr, addr2, sizeof(addr)) != 0) {
diag_printf("Ethernet FEC MAC address from fconfig: ");
diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
if (cyg_plf_redboot_esa_validate(addr)) {
diag_printf("** Error: Invalid MAC address: ");
diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
#ifdef SOC_MAC_ADDR_LOCK_BIT
if ((readl(SOC_MAC_ADDR_BASE - 0x68) & SOC_MAC_ADDR_LOCK_BIT) == 0) {
}
static mxc_fec_priv_t mxc_fec_private = {
- .phy = ð0_phy, // PHY access routines
+ .phy = ð0_phy, // PHY access routines
.provide_esa = _tx25_provide_fec_esa,
};
ETH_DRV_SC(mxc_fec_sc,
&mxc_fec_private, // Driver specific data
- mxc_fec_name,
- mxc_fec_start,
- mxc_fec_stop,
- mxc_fec_control,
- mxc_fec_can_send,
- mxc_fec_send,
- mxc_fec_recv,
- mxc_fec_deliver, // "pseudoDSR" called from fast net thread
- mxc_fec_poll, // poll function, encapsulates ISR and DSR
- mxc_fec_int_vector);
+ mxc_fec_name,
+ mxc_fec_start,
+ mxc_fec_stop,
+ mxc_fec_control,
+ mxc_fec_can_send,
+ mxc_fec_send,
+ mxc_fec_recv,
+ mxc_fec_deliver, // "pseudoDSR" called from fast net thread
+ mxc_fec_poll, // poll function, encapsulates ISR and DSR
+ mxc_fec_int_vector);
NETDEVTAB_ENTRY(mxc_fec_netdev,
- mxc_fec_name,
- tx25_fec_init,
- &mxc_fec_sc);
+ mxc_fec_name,
+ tx25_fec_init,
+ &mxc_fec_sc);
#endif
#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
RedBoot_config_option("Set FEC network hardware address [MAC]",
- fec_esa,
- ALWAYS_ENABLED, true,
- CONFIG_BOOL, false
- );
+ fec_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_BOOL, true
+ );
RedBoot_config_option("FEC network hardware address [MAC]",
- fec_esa_data,
- "fec_esa", true,
- CONFIG_ESA, 0
- );
+ fec_esa_data,
+ "fec_esa", true,
+ CONFIG_ESA, 0
+ );
#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT