#define FEC_BD_RX_NUM 256
#define FEC_BD_TX_NUM 2
-#ifdef CYGOPT_HAL_ARM_MXC_FEC_MIIGSK
+#ifdef CYGPKG_HAL_ARM_MX25
/* the defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define erdsr 0x180 /*Pointer to Receive Descriptor Ring*/
#define etdsr 0x184 /*Pointer to Transmit Descriptor Ring*/
#define emrbr 0x188 /*Maximum Receive Buffer size*/
-#ifdef CYGOPT_HAL_ARM_MXC_FEC_MIIGSK
+#ifdef CYGPKG_HAL_ARM_MX25
#define miigsk_cfgr 0x300 /* MIIGSK Configuration Register */
#define miigsk_enr 0x308 /* MIIGSK Enable Register */
#endif