static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
{
- if (((virt & 0xF0000000) == CSD0_BASE_ADDR) ||
- ((virt & 0xF0000000) == UNCACHED_RAM_BASE_VIRT)) {
- virt &= ~0xF0000000;
+ if (((virt & 0xf0000000) >= CSD0_BASE_ADDR) &&
+ ((virt & 0xf0000000) < CSD0_BASE_ADDR + SDRAM_SIZE)) {
+ virt -= CSD0_BASE_ADDR;
+ } else if (((virt & 0xf0000000) >= UNCACHED_RAM_BASE_VIRT) &&
+ ((virt & 0xf0000000) < UNCACHED_RAM_BASE_VIRT + SDRAM_SIZE)) {
+ virt -= UNCACHED_RAM_BASE_VIRT;
}
- if (virt < SDRAM_SIZE) {
- return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
+ if (virt < RAM_BANK0_SIZE) {
+ return virt + CSD0_BASE_ADDR;
+ } else if (virt < SDRAM_SIZE) {
+ return virt - RAM_BANK0_SIZE + CSD1_BASE_ADDR;
}
- if ((virt & 0xF0000000) == UNCACHED_RAM_BASE_VIRT) {
- if (virt >= RAM_BANK0_SIZE) {
- virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
- }
- }
- return virt;
+ return ~0;
}
/*
/* 0xb0000000 .. (0xb0000000 + SDRAM_SIZE) is
* uncacheable memory space which is mapped to SDRAM
*/
- if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
- phy = (phy - CSD0_BASE_ADDR) | UNCACHED_RAM_BASE_VIRT;
- }
- if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
- phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | UNCACHED_RAM_BASE_VIRT;
+ if (((phy & 0xF0000000) >= CSD0_BASE_ADDR) &&
+ ((phy & 0xF0000000) < CSD0_BASE_ADDR + RAM_BANK0_SIZE)) {
+ return (phy - CSD0_BASE_ADDR) + UNCACHED_RAM_BASE_VIRT;
+#ifdef RAM_BANK1_SIZE
+ } else if (((phy & 0xF0000000) >= CSD1_BASE_ADDR) &&
+ ((phy & 0xF0000000) < CSD1_BASE_ADDR + RAM_BANK1_SIZE)) {
+ return (phy - CSD1_BASE_ADDR + RAM_BANK0_SIZE) + UNCACHED_RAM_BASE_VIRT;
+#endif
}
- return phy;
+ return ~0;
}
#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H