unsigned short retry, tmo;
unsigned long data;
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
- au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
+ __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
AC97_CDC(pscdata));
- au_sync();
+ wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
- if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
- data = au_readl(AC97_CDC(pscdata));
+ data = __raw_readl(AC97_CDC(pscdata));
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
unsigned int tmo, retry;
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
- au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
+ __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
AC97_CDC(pscdata));
- au_sync();
+ wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
- if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
} while (--retry && !tmo);
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
- au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
msleep(10);
- au_writel(0, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(0, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
}
static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
int i;
/* disable PSC during cold reset */
- au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
/* issue cold reset */
- au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
msleep(500);
- au_writel(0, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(0, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
/* enable PSC */
- au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for PSC to indicate it's ready */
i = 1000;
- while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
msleep(1);
if (i == 0) {
}
/* enable the ac97 function */
- au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for AC97 core to become ready */
i = 1000;
- while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
msleep(1);
if (i == 0)
printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
chans = params_channels(params);
- r = ro = au_readl(AC97_CFG(pscdata));
- stat = au_readl(AC97_STAT(pscdata));
+ r = ro = __raw_readl(AC97_CFG(pscdata));
+ stat = __raw_readl(AC97_STAT(pscdata));
/* already active? */
if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
mutex_lock(&pscdata->lock);
/* disable AC97 device controller first... */
- au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...wait for it... */
t = 100;
- while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
+ while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
msleep(1);
if (!t)
printk(KERN_ERR "PSC-AC97: can't disable!\n");
/* ...write config... */
- au_writel(r, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...enable the AC97 controller again... */
- au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...and wait for ready bit */
t = 100;
- while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
+ while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
msleep(1);
if (!t)
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
- au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
- au_sync();
- au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
- au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
- while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
+ while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
asm volatile ("nop");
- au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
break;
default:
PSC_AC97CFG_DE_ENABLE;
/* preserve PSC clock source set up by platform */
- sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
- au_writel(0, PSC_SEL(wd));
- au_sync();
- au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
- au_sync();
+ sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(0, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
snd_soc_unregister_component(&pdev->dev);
/* disable PSC completely */
- au_writel(0, AC97_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, AC97_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
au1xpsc_ac97_workdata = NULL; /* MDEV */
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* save interesting registers and disable PSC */
- wd->pm[0] = au_readl(PSC_SEL(wd));
+ wd->pm[0] = __raw_readl(PSC_SEL(wd));
- au_writel(0, AC97_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, AC97_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
return 0;
}
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* restore PSC clock config */
- au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
- au_sync();
+ __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
/* after this point the ac97 core will cold-reset the codec.
* During cold-reset the PSC is reinitialized and the last