X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;ds=sidebyside;f=packages%2Fhal%2Farm%2Fmx37%2Fvar%2Fv2_0%2Finclude%2Fhal_cache.h;h=1550a8ba424fd1a094aa49e12e094b41b31397cd;hb=6bb42bcdf232113f4d0c7967594780be176a03cd;hp=2e5798735d151b2c36df916dfc6124a11a2ee164;hpb=583b78b1346e198b59031c5816fdeb83f1b79fe7;p=karo-tx-redboot.git diff --git a/packages/hal/arm/mx37/var/v2_0/include/hal_cache.h b/packages/hal/arm/mx37/var/v2_0/include/hal_cache.h index 2e579873..1550a8ba 100644 --- a/packages/hal/arm/mx37/var/v2_0/include/hal_cache.h +++ b/packages/hal/arm/mx37/var/v2_0/include/hal_cache.h @@ -43,234 +43,234 @@ //============================================================================= #include -#include // Variant specific hardware definitions +#include // Variant specific hardware definitions //----------------------------------------------------------------------------- // Cache dimensions // Data cache -#define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line -#define HAL_DCACHE_WAYS 64 // Associativity of the cache +#define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line +#define HAL_DCACHE_WAYS 64 // Associativity of the cache // Instruction cache -#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line -#define HAL_ICACHE_WAYS 64 // Associativity of the cache +#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line +#define HAL_ICACHE_WAYS 64 // Associativity of the cache #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE / (HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE / (HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX -#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20 +#define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100 //----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache -#define HAL_DCACHE_ENABLE_L1() \ -CYG_MACRO_START \ - asm volatile ( \ - "mrc p15, 0, r1, c1, c0, 0;" \ - "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \ - /* the MMU, alignment faults, and */ \ - "mcr p15, 0, r1, c1, c0, 0" \ - : \ - : \ - : "r1" /* Clobber list */ \ - ); \ +#define HAL_DCACHE_ENABLE_L1() \ +CYG_MACRO_START \ + asm volatile ( \ + "mrc p15, 0, r1, c1, c0, 0;" \ + "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \ + /* the MMU, alignment faults, and */ \ + "mcr p15, 0, r1, c1, c0, 0" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ CYG_MACRO_END // Disable the data cache -#define HAL_DCACHE_DISABLE_L1() \ -CYG_MACRO_START \ - asm volatile ( \ - "mov r1, #0;" \ - "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */ \ - "mrc p15, 0, r1, c1, c0, 0;" \ - "bic r1, r1, #0x0004;" /* disable DCache */ \ - /* but not MMU and alignment faults */ \ - "mcr p15, 0, r1, c1, c0, 0" \ - : \ - : \ - : "r1" /* Clobber list */ \ - ); \ +#define HAL_DCACHE_DISABLE_L1() \ +CYG_MACRO_START \ + asm volatile ( \ + "mov r1, #0;" \ + "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */ \ + "mrc p15, 0, r1, c1, c0, 0;" \ + "bic r1, r1, #0x0004;" /* disable DCache */ \ + /* but not MMU and alignment faults */ \ + "mcr p15, 0, r1, c1, c0, 0" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ CYG_MACRO_END // Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL_L1() \ -CYG_MACRO_START /* this macro can discard dirty cache lines. */ \ - asm volatile ( \ - "mov r0, #0;" \ - "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ \ - "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ \ - : \ - : \ - : "r0","memory" /* clobber list */ \ - ); \ +#define HAL_DCACHE_INVALIDATE_ALL_L1() \ +CYG_MACRO_START /* this macro can discard dirty cache lines. */ \ + asm volatile ( \ + "mov r0, #0;" \ + "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ \ + "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ \ + : \ + : \ + : "r0","memory" /* clobber list */ \ + ); \ CYG_MACRO_END // Synchronize the contents of the cache with memory. // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX) -#define HAL_DCACHE_SYNC_L1() \ -CYG_MACRO_START \ - asm volatile ( \ - "nop; " \ - "nop; " \ - "nop; " \ - "nop; " \ - "nop; " \ - "nop; " \ - "mov r0, #0x0;" \ - "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/ \ - "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \ - "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */ \ - : \ - : \ - : "r0" /* Clobber list */ \ - ); \ +#define HAL_DCACHE_SYNC_L1() \ +CYG_MACRO_START \ + asm volatile ( \ + "nop; " \ + "nop; " \ + "nop; " \ + "nop; " \ + "nop; " \ + "nop; " \ + "mov r0, #0x0;" \ + "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/ \ + "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \ + "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */ \ + : \ + : \ + : "r0" /* Clobber list */ \ + ); \ CYG_MACRO_END // Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) \ -CYG_MACRO_START \ - register int reg; \ - asm volatile ( \ - "nop; " \ - "nop; " \ - "nop; " \ - "nop; " \ - "nop; " \ - "mrc p15, 0, %0, c1, c0, 0;" \ - : "=r"(reg) \ - : \ - ); \ - (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \ +#define HAL_DCACHE_IS_ENABLED(_state_) \ +CYG_MACRO_START \ + register int reg; \ + asm volatile ( \ + "nop; " \ + "nop; " \ + "nop; " \ + "nop; " \ + "nop; " \ + "mrc p15, 0, %0, c1, c0, 0;" \ + : "=r"(reg) \ + : \ + ); \ + (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \ CYG_MACRO_END //----------------------------------------------------------------------------- // Global control of Instruction cache // Enable the instruction cache -#define HAL_ICACHE_ENABLE_L1() \ -CYG_MACRO_START \ - asm volatile ( \ - "mrc p15, 0, r1, c1, c0, 0;" \ - "orr r1, r1, #0x1000;" \ - "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \ - /* that MMU and alignment faults */ \ - /* are enabled) */ \ - "mcr p15, 0, r1, c1, c0, 0" \ - : \ - : \ - : "r1" /* Clobber list */ \ - ); \ +#define HAL_ICACHE_ENABLE_L1() \ +CYG_MACRO_START \ + asm volatile ( \ + "mrc p15, 0, r1, c1, c0, 0;" \ + "orr r1, r1, #0x1000;" \ + "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \ + /* that MMU and alignment faults */ \ + /* are enabled) */ \ + "mcr p15, 0, r1, c1, c0, 0" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ CYG_MACRO_END // Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) \ -CYG_MACRO_START \ - register cyg_uint32 reg; \ - asm volatile ( \ - "mrc p15, 0, %0, c1, c0, 0" \ - : "=r"(reg) \ - : \ - ); \ - \ - (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \ +#define HAL_ICACHE_IS_ENABLED(_state_) \ +CYG_MACRO_START \ + register cyg_uint32 reg; \ + asm volatile ( \ + "mrc p15, 0, %0, c1, c0, 0" \ + : "=r"(reg) \ + : \ + ); \ + \ + (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \ CYG_MACRO_END // Disable the instruction cache -#define HAL_ICACHE_DISABLE_L1() \ -CYG_MACRO_START \ - asm volatile ( \ - "mrc p15, 0, r1, c1, c0, 0;" \ - "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \ - "mcr p15, 0, r1, c1, c0, 0;" \ - "mov r1, #0;" \ - "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \ - "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \ - "nop;" /* next few instructions may be via cache */ \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop" \ - : \ - : \ - : "r1" /* Clobber list */ \ - ); \ +#define HAL_ICACHE_DISABLE_L1() \ +CYG_MACRO_START \ + asm volatile ( \ + "mrc p15, 0, r1, c1, c0, 0;" \ + "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \ + "mcr p15, 0, r1, c1, c0, 0;" \ + "mov r1, #0;" \ + "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \ + "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \ + "nop;" /* next few instructions may be via cache */ \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ CYG_MACRO_END // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL_L1() \ -CYG_MACRO_START \ - /* this macro can discard dirty cache lines (N/A for ICache) */ \ - asm volatile ( \ - "mov r1, #0;" \ - "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \ - "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \ - "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \ - "nop;" /* next few instructions may be via cache */ \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - : \ - : \ - : "r1" /* Clobber list */ \ - ); \ +#define HAL_ICACHE_INVALIDATE_ALL_L1() \ +CYG_MACRO_START \ + /* this macro can discard dirty cache lines (N/A for ICache) */ \ + asm volatile ( \ + "mov r1, #0;" \ + "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \ + "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \ + "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \ + "nop;" /* next few instructions may be via cache */ \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ CYG_MACRO_END // Synchronize the contents of the cache with memory. // (which includes flushing out pending writes) -#define HAL_ICACHE_SYNC() \ -CYG_MACRO_START \ - HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \ - HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \ +#define HAL_ICACHE_SYNC() \ +CYG_MACRO_START \ + HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \ + HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \ CYG_MACRO_END // Query the state of the L2 cache -#define HAL_L2CACHE_IS_ENABLED(_state_) \ - (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) +#define HAL_L2CACHE_IS_ENABLED(_state_) \ + (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) #ifdef L2CC_ENABLED -#define HAL_ENABLE_L2() \ -{ \ - writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \ +#define HAL_ENABLE_L2() \ +{ \ + writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \ } -#define HAL_DISABLE_L2() \ -{ \ - writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \ +#define HAL_DISABLE_L2() \ +{ \ + writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG); \ } -#define HAL_SYNC_L2() \ -{ \ - if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ - writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG); \ - while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1); \ - } \ +#define HAL_SYNC_L2() \ +{ \ + if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ + writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG); \ + while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1); \ + } \ } -#define HAL_INVALIDATE_L2() \ -{ \ - if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ - writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG); \ - while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0); \ - HAL_SYNC_L2(); \ - } \ +#define HAL_INVALIDATE_L2() \ +{ \ + if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ + writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG); \ + while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0); \ + HAL_SYNC_L2(); \ + } \ } - \ -#define HAL_CLEAN_INVALIDATE_L2() \ -{ \ - if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ - writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG); \ - while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\ - HAL_SYNC_L2(); \ - } \ + \ +#define HAL_CLEAN_INVALIDATE_L2() \ +{ \ + if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) { \ + writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG); \ + while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\ + HAL_SYNC_L2(); \ + } \ } #else //L2CC_ENABLED @@ -284,38 +284,38 @@ CYG_MACRO_END /*********************** Exported macros *******************/ -#define HAL_DCACHE_ENABLE() { \ - HAL_DCACHE_ENABLE_L1(); \ - HAL_ENABLE_L2(); \ +#define HAL_DCACHE_ENABLE() { \ + HAL_DCACHE_ENABLE_L1(); \ + HAL_ENABLE_L2(); \ } -#define HAL_DCACHE_DISABLE() { \ - HAL_DCACHE_DISABLE_L1(); \ - HAL_DISABLE_L2(); \ +#define HAL_DCACHE_DISABLE() { \ + HAL_DCACHE_DISABLE_L1(); \ + HAL_DISABLE_L2(); \ } -#define HAL_DCACHE_INVALIDATE_ALL() { \ - HAL_DCACHE_INVALIDATE_ALL_L1(); \ - HAL_CLEAN_INVALIDATE_L2(); \ +#define HAL_DCACHE_INVALIDATE_ALL() { \ + HAL_DCACHE_INVALIDATE_ALL_L1(); \ + HAL_CLEAN_INVALIDATE_L2(); \ } -#define HAL_DCACHE_SYNC() { \ - HAL_DCACHE_SYNC_L1(); \ - /* don't just call HAL_SYNC_L2() */ \ - HAL_CLEAN_INVALIDATE_L2(); \ +#define HAL_DCACHE_SYNC() { \ + HAL_DCACHE_SYNC_L1(); \ + /* don't just call HAL_SYNC_L2() */ \ + HAL_CLEAN_INVALIDATE_L2(); \ } -#define HAL_ICACHE_INVALIDATE_ALL() { \ - HAL_ICACHE_INVALIDATE_ALL_L1(); \ - HAL_CLEAN_INVALIDATE_L2(); \ +#define HAL_ICACHE_INVALIDATE_ALL() { \ + HAL_ICACHE_INVALIDATE_ALL_L1(); \ + HAL_CLEAN_INVALIDATE_L2(); \ } -#define HAL_ICACHE_DISABLE() { \ - HAL_ICACHE_DISABLE_L1(); \ -} +#define HAL_ICACHE_DISABLE() { \ + HAL_ICACHE_DISABLE_L1(); \ +} -#define HAL_ICACHE_ENABLE() { \ - HAL_ICACHE_ENABLE_L1(); \ +#define HAL_ICACHE_ENABLE() { \ + HAL_ICACHE_ENABLE_L1(); \ } #endif // ifndef CYGONCE_HAL_CACHE_H