X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=arch%2Farm%2Fboot%2Fdts%2Farmada-xp-db.dts;h=e37863f826b942d0aef2aa55a60c1fb2318f538d;hb=82a682676ce34e59369f60168a8729348aaae4d0;hp=e83505e4c236c242eeb13c1094961b622a7646a8;hpb=d3c926264a92e5ea448add3e883530e1edad3ce2;p=karo-tx-linux.git

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..e37863f826b9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,24 +30,24 @@
 	};
 
 	soc {
-		serial@d0012000 {
+		serial@12000 {
 			clock-frequency = <250000000>;
 			status = "okay";
 		};
-		serial@d0012100 {
+		serial@12100 {
 			clock-frequency = <250000000>;
 			status = "okay";
 		};
-		serial@d0012200 {
+		serial@12200 {
 			clock-frequency = <250000000>;
 			status = "okay";
 		};
-		serial@d0012300 {
+		serial@12300 {
 			clock-frequency = <250000000>;
 			status = "okay";
 		};
 
-		sata@d00a0000 {
+		sata@a0000 {
 			nr-ports = <2>;
 			status = "okay";
 		};
@@ -70,47 +70,47 @@
 			};
 		};
 
-		ethernet@d0070000 {
+		ethernet@70000 {
 			status = "okay";
 			phy = <&phy0>;
 			phy-mode = "rgmii-id";
 		};
-		ethernet@d0074000 {
+		ethernet@74000 {
 			status = "okay";
 			phy = <&phy1>;
 			phy-mode = "rgmii-id";
 		};
-		ethernet@d0030000 {
+		ethernet@30000 {
 			status = "okay";
 			phy = <&phy2>;
 			phy-mode = "sgmii";
 		};
-		ethernet@d0034000 {
+		ethernet@34000 {
 			status = "okay";
 			phy = <&phy3>;
 			phy-mode = "sgmii";
 		};
 
-		mvsdio@d00d4000 {
+		mvsdio@d4000 {
 			pinctrl-0 = <&sdio_pins>;
 			pinctrl-names = "default";
 			status = "okay";
 			/* No CD or WP GPIOs */
 		};
 
-		usb@d0050000 {
+		usb@50000 {
 			status = "okay";
 		};
 
-		usb@d0051000 {
+		usb@51000 {
 			status = "okay";
 		};
 
-		usb@d0052000 {
+		usb@52000 {
 			status = "okay";
 		};
 
-		spi0: spi@d0010600 {
+		spi0: spi@10600 {
 			status = "okay";
 
 			spi-flash@0 {
@@ -121,5 +121,38 @@
 				spi-max-frequency = <20000000>;
 			};
 		};
+
+		pcie-controller {
+			status = "okay";
+
+			/*
+			 * All 6 slots are physically present as
+			 * standard PCIe slots on the board.
+			 */
+			pcie@1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+			pcie@2,0 {
+				/* Port 0, Lane 1 */
+				status = "okay";
+			};
+			pcie@3,0 {
+				/* Port 0, Lane 2 */
+				status = "okay";
+			};
+			pcie@4,0 {
+				/* Port 0, Lane 3 */
+				status = "okay";
+			};
+			pcie@9,0 {
+				/* Port 2, Lane 0 */
+				status = "okay";
+			};
+			pcie@10,0 {
+				/* Port 3, Lane 0 */
+				status = "okay";
+			};
+		};
 	};
 };