X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx5%2Fimx-regs.h;h=091055f8f07fb723f9fbb07a3acc802bcd008059;hb=8f02caac64980faa73b2bf00462b400c86257d04;hp=8117f4f91aed0872fe45a2b96b10efda96850c36;hpb=d978780b2e676c005460cd561f4f15b5220bdf49;p=karo-tx-uboot.git

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 8117f4f91a..091055f8f0 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -1,50 +1,34 @@
 /*
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
 #define __ASM_ARCH_MX5_IMX_REGS_H__
 
+#define ARCH_MXC
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
 #define IPU_SOC_BASE_ADDR	0x40000000
-#define IPU_SOC_OFFSET		0x1E000000
-#define SPBA0_BASE_ADDR         0x70000000
-#define AIPS1_BASE_ADDR         0x73F00000
-#define AIPS2_BASE_ADDR         0x83F00000
-#define CSD0_BASE_ADDR          0x90000000
-#define CSD1_BASE_ADDR          0xA0000000
-#define NFC_BASE_ADDR_AXI       0xCFFF0000
-#define CS1_BASE_ADDR           0xB8000000
+#define SPBA0_BASE_ADDR		0x70000000
+#define AIPS1_BASE_ADDR		0x73F00000
+#define AIPS2_BASE_ADDR		0x83F00000
+#define CSD0_BASE_ADDR		0x90000000
+#define CSD1_BASE_ADDR		0xA0000000
+#define NFC_BASE_ADDR_AXI	0xCFFF0000
+#define CS1_BASE_ADDR		0xB8000000
 #elif defined(CONFIG_MX53)
-#define IPU_SOC_BASE_ADDR	0x18000000
-#define IPU_SOC_OFFSET		0x06000000
-#define SPBA0_BASE_ADDR         0x50000000
-#define AIPS1_BASE_ADDR         0x53F00000
-#define AIPS2_BASE_ADDR         0x63F00000
-#define CSD0_BASE_ADDR          0x70000000
-#define CSD1_BASE_ADDR          0xB0000000
-#define NFC_BASE_ADDR_AXI       0xF7FF0000
-#define IRAM_BASE_ADDR          0xF8000000
-#define CS1_BASE_ADDR           0xF4000000
+#define IPU_SOC_BASE_ADDR	0x00000000
+#define SPBA0_BASE_ADDR		0x50000000
+#define AIPS1_BASE_ADDR		0x53F00000
+#define AIPS2_BASE_ADDR		0x63F00000
+#define CSD0_BASE_ADDR		0x70000000
+#define CSD1_BASE_ADDR		0xB0000000
+#define NFC_BASE_ADDR_AXI	0xF7FF0000
+#define IRAM_BASE_ADDR		0xF8000000
+#define CS1_BASE_ADDR		0xF4000000
 #define SATA_BASE_ADDR		0x10000000
 #else
 #error "CPU_TYPE not defined"
@@ -58,7 +42,7 @@
 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
@@ -93,10 +77,11 @@
 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
 
 #if defined(CONFIG_MX53)
-#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
-#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
+#define GPIO5_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000E4000)
+#define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
+#define UART4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000F0000)
 #endif
 /*
  * AIPS 2
@@ -111,7 +96,7 @@
 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A4000)
 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
@@ -138,7 +123,7 @@
 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
 
 #if defined(CONFIG_MX53)
-#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#define UART5_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00090000)
 #endif
 
 /*
@@ -215,21 +200,6 @@
  */
 #define WBED		1
 
-/*
- * WEIM WCR
- */
-#define BCM		1
-#define GBCD(x)		(((x) & 0x3) << 1)
-#define INTEN		(1 << 4)
-#define INTPOL		(1 << 5)
-#define WDOG_EN		(1 << 8)
-#define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
-
-#define CS0_128					0
-#define CS0_64M_CS1_64M				1
-#define CS0_64M_CS1_32M_CS2_32M			2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
-
 /*
  * CSPI register definitions
  */
@@ -237,6 +207,7 @@
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
 #define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK	(0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
@@ -252,9 +223,10 @@
 #define MXC_CSPICTRL_CHAN	18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #define MXC_SPI_BASE_ADDRESSES \
 	CSPI1_BASE_ADDR, \
 	CSPI2_BASE_ADDR, \
@@ -263,7 +235,7 @@
 /*
  * Number of GPIO pins per port
  */
-#define GPIO_NUM_PIN            32
+#define GPIO_NUM_PIN	32
 
 #define IIM_SREV	0x24
 #define ROM_SI_REV	0x48
@@ -273,6 +245,8 @@
 /* M4IF */
 #define M4IF_FBPM0	0x40
 #define M4IF_FIDBP	0x48
+#define M4IF_GENP_WEIM_MM_MASK		0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000
 
 /* Assuming 24MHz input clock with doubler ON */
 /*                            MFI         PDF */
@@ -297,28 +271,46 @@
 #define DP_MFD_665	(96 - 1)
 #define DP_MFN_665	89
 
+#define DP_OP_600       ((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_600      (4 - 1)
+#define DP_MFN_600      1
+
 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_532	(24 - 1)
 #define DP_MFN_532	13
 
+#define DP_OP_533	((5 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_533	(9 - 1)
+#define DP_MFN_533	5
+
+#define DP_OP_455	((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455	(48 - 1)
+#define DP_MFN_455	23
+
 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
 #define DP_MFD_400	(3 - 1)
 #define DP_MFN_400	1
 
+#define DP_OP_333	((6 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_333	(16 - 1)
+#define DP_MFN_333	15
+
 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
 #define DP_MFD_216	(4 - 1)
 #define DP_MFN_216	3
 
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5		0x25
-#define CHIP_REV_3_0            0x30
+#define CHIP_REV_1_0	0x10
+#define CHIP_REV_1_1	0x11
+#define CHIP_REV_2_0	0x20
+#define CHIP_REV_2_5	0x25
+#define CHIP_REV_3_0	0x30
+
+#define BOARD_REV_1_0	0x0
+#define BOARD_REV_2_0	0x1
 
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
+#define BOARD_VER_OFFSET	0x8
 
-#define IMX_IIM_BASE            (IIM_BASE_ADDR)
+#define IMX_IIM_BASE	IIM_BASE_ADDR
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
@@ -427,8 +419,7 @@ struct weim {
 
 #if defined(CONFIG_MX51)
 struct iomuxc {
-	u32	gpr0;
-	u32	gpr1;
+	u32	gpr[2];
 	u32	omux0;
 	u32	omux1;
 	u32	omux2;
@@ -437,9 +428,7 @@ struct iomuxc {
 };
 #elif defined(CONFIG_MX53)
 struct iomuxc {
-	u32	gpr0;
-	u32	gpr1;
-	u32	gpr2;
+	u32	gpr[3];
 	u32	omux0;
 	u32	omux1;
 	u32	omux2;
@@ -458,6 +447,24 @@ struct src {
 	u32	simr;
 };
 
+struct srtc_regs {
+	u32	lpscmr;		/* 0x00 */
+	u32	lpsclr;		/* 0x04 */
+	u32	lpsar;		/* 0x08 */
+	u32	lpsmcr;		/* 0x0c */
+	u32	lpcr;		/* 0x10 */
+	u32	lpsr;		/* 0x14 */
+	u32	lppdr;		/* 0x18 */
+	u32	lpgr;		/* 0x1c */
+	u32	hpcmr;		/* 0x20 */
+	u32	hpclr;		/* 0x24 */
+	u32	hpamr;		/* 0x28 */
+	u32	hpalr;		/* 0x2c */
+	u32	hpcr;		/* 0x30 */
+	u32	hpisr;		/* 0x34 */
+	u32	hpienr;		/* 0x38 */
+};
+
 /* CSPI registers */
 struct cspi_regs {
 	u32 rxdata;
@@ -473,7 +480,7 @@ struct cspi_regs {
 struct iim_regs {
 	u32	stat;
 	u32	statm;
-	u32     err;
+	u32	err;
 	u32	emask;
 	u32	fctl;
 	u32	ua;
@@ -490,12 +497,22 @@ struct iim_regs {
 	struct fuse_bank {
 		u32	fuse_regs[0x20];
 		u32	fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
 	} bank[4];
+#elif defined(CONFIG_MX53)
+	} bank[5];
+#endif
 };
 
 struct fuse_bank0_regs {
-	u32	fuse0_23[24];
+	u32	fuse0_7[8];
+	u32	uid[8];
+	u32	fuse16_23[8];
+#if defined(CONFIG_MX51)
+	u32	imei[8];
+#elif defined(CONFIG_MX53)
 	u32	gp[8];
+#endif
 };
 
 struct fuse_bank1_regs {
@@ -504,6 +521,14 @@ struct fuse_bank1_regs {
 	u32	fuse15_31[0x11];
 };
 
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+	u32	fuse0_4[5];
+	u32	gp[3];
+	u32	fuse8_31[0x18];
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */