X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-zynqmp%2Fhardware.h;h=0f03c246d72d79de33d87b45bad691dda24285d7;hb=160bfd37622c47791d65fcfabddd401004d88d37;hp=188b5c2144af73058083ed0ac27bac389fdedfa7;hpb=29a447f2ccc6d044d10400bf1b9efbfe7d632014;p=karo-tx-uboot.git

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 188b5c2144..0f03c246d7 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -11,9 +11,25 @@
 #define ZYNQ_SERIAL_BASEADDR0	0xFF000000
 #define ZYNQ_SERIAL_BASEADDR1	0xFF001000
 
+#define ZYNQ_GEM_BASEADDR0	0xFF0B0000
+#define ZYNQ_GEM_BASEADDR1	0xFF0C0000
+#define ZYNQ_GEM_BASEADDR2	0xFF0D0000
+#define ZYNQ_GEM_BASEADDR3	0xFF0E0000
+
+#define ZYNQ_SPI_BASEADDR0	0xFF040000
+#define ZYNQ_SPI_BASEADDR1	0xFF050000
+
+#define ZYNQ_I2C_BASEADDR0	0xFF020000
+#define ZYNQ_I2C_BASEADDR1	0xFF030000
+
 #define ZYNQ_SDHCI_BASEADDR0	0xFF160000
 #define ZYNQ_SDHCI_BASEADDR1	0xFF170000
 
+#define ZYNQMP_SATA_BASEADDR	0xFD0C0000
+
+#define ZYNQMP_USB0_XHCI_BASEADDR	0xFE200000
+#define ZYNQMP_USB1_XHCI_BASEADDR	0xFE300000
+
 #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
 
@@ -31,7 +47,11 @@ struct crlapb_regs {
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
 
+#if defined(CONFIG_SECURE_IOU)
+#define ZYNQMP_IOU_SCNTR	0xFF260000
+#else
 #define ZYNQMP_IOU_SCNTR	0xFF250000
+#endif
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
 
@@ -45,9 +65,19 @@ struct iou_scntr {
 
 /* Bootmode setting values */
 #define BOOT_MODES_MASK	0x0000000F
-#define SD_MODE		0x00000005
+#define SD_MODE		0x00000003
+#define EMMC_MODE	0x00000006
 #define JTAG_MODE	0x00000000
 
+#define ZYNQMP_IOU_SLCR_BASEADDR	0xFF180000
+
+struct iou_slcr_regs {
+	u32 mio_pin[78];
+	u32 reserved[442];
+};
+
+#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
+
 #define ZYNQMP_RPU_BASEADDR	0xFF9A0000
 
 struct rpu_regs {