X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=arch%2Farm%2Fmach-mv78xx0%2Finclude%2Fmach%2Fmv78xx0.h;fp=arch%2Farm%2Fmach-mv78xx0%2Finclude%2Fmach%2Fmv78xx0.h;h=8bb402f7f8ecce51cfae84e80fe41571ec6f367b;hb=291b7c3a02a7eafbb8ea89a2c0e93676d6972926;hp=788bdace13048a55192303d31d243b8521a79d93;hpb=f639011b4020a8230c8d09866f6eaadcb12e8dde;p=mv-sheeva.git

diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 788bdace130..8bb402f7f8e 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -52,9 +52,18 @@
 #define MV78XX0_REGS_VIRT_BASE		0xfef00000
 #define MV78XX0_REGS_SIZE		SZ_1M
 
+#define MV78XX0_SRAM_PHYS_BASE		0xf4000000
+#define MV78XX0_SRAM_SIZE		SZ_2K
+
 #define MV78XX0_PCIE_MEM_PHYS_BASE	0xc0000000
 #define MV78XX0_PCIE_MEM_SIZE		0x30000000
 
+#define MV78XX0_NAND_MEM_PHYS_BASE	0xfa000000
+#define MV78XX0_NAND_MEM_SIZE		SZ_1K
+
+#define MV78XX0_BOOTCS_MEM_PHY_BASE	0xfc000000
+#define MV78XX0_BOOTCS_MEM_SIZE		SZ_64M
+
 /*
  * Core-specific peripheral registers.
  */
@@ -71,6 +80,7 @@
 #define DEV_BUS_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET_LOW	(DEV_BUS_VIRT_BASE | 0x0030)
 #define  SAMPLE_AT_RESET_HIGH	(DEV_BUS_VIRT_BASE | 0x0034)
+#define  SPI_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1000)
 #define  I2C_1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2000)
@@ -94,6 +104,11 @@
 #define USB1_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0x51000)
 #define USB2_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0x52000)
 
+#define XOR0_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0x60900)
+#define XOR0_VIRT_BASE		(MV78XX0_REGS_VIRT_BASE | 0x60900)
+#define XOR0_HIGH_PHYS_BASE	(MV78XX0_REGS_PHYS_BASE | 0x60B00)
+#define XOR0_HIGH_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE | 0x60B00)
+
 #define GE00_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0x70000)
 #define GE01_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0x74000)
 
@@ -102,6 +117,8 @@
 #define PCIE12_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE | 0x88000)
 #define PCIE13_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE | 0x8c000)
 
+#define CRYPTO_PHYS_BASE	(MV78XX0_REGS_PHYS_BASE | 0x90000)
+
 #define SATA_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE | 0xa0000)
 
 /*