X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Flowlevel_init.S;h=049d99ba641c2115c62c779b0394a93dbf34bad2;hb=02e0d243b17007d5248df08260163ee6e706aad7;hp=027db9aa9e25031013e1cc1f24cbdd3692ec4e42;hpb=5991b7ed19f0a899c6eb97533ca0c8bd9a6fcd81;p=karo-tx-uboot.git diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 027db9aa9e..049d99ba64 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -17,25 +17,42 @@ #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK #ifdef PHYS_SDRAM_2_SIZE -#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define SDRAM_SIZE ((PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) / SZ_1M) #else -#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE / SZ_1M) #endif +#define BIT(x) (1 << (x)) +#define CCGR(m) (3 << ((m) * 2)) + #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ (((l) >> 8) & 0x0000FF00) | \ (((l) >> 24) & 0x000000FF)) -#define CHECK_DCD_ADDR(a) ( \ +#ifndef CONFIG_TX6QP +#define CHECK_DCD_ADDR(a) ( \ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ - ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ - ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ - ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */) +#else +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ + ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */ || \ + ((a) >= 0x00BB0000 && (a) <= 0x00BB003F) /* NoC DDR config */) +#endif .macro mxc_dcd_item addr, val .ifne CHECK_DCD_ADDR(\addr) @@ -46,22 +63,22 @@ .endm #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val) -#if PHYS_SDRAM_1_WIDTH == 16 -#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val) +#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16 +#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) #else #define MXC_DCD_ITEM_16(addr, val) #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) #endif -#if PHYS_SDRAM_1_WIDTH > 16 -#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val) +#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16 +#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) #else #define MXC_DCD_ITEM_32(addr, val) #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) #endif -#if PHYS_SDRAM_1_WIDTH == 64 -#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val) +#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64 +#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) #else #define MXC_DCD_ITEM_64(addr, val) @@ -111,6 +128,8 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) +#define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max .iflt \clks - \offs @@ -161,7 +180,7 @@ dcd_end: #define ADDR_MIRROR 0 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3 -/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */ #if SDRAM_CLK > 666 && SDRAM_CLK <= 800 #define CL_VAL 11 #define CWL_VAL 8 @@ -181,19 +200,54 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE < 2048 +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ +CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ +NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */ +CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ + +/* MDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#else +/* 4096MiB SDRAM: IM4G16D3EABG-125I */ +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ /* MDCFG1 0x10 */ -CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ -CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ -NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ @@ -203,16 +257,18 @@ CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ -CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#endif + #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) /* MDOTC 0x08 */ -CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ -CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ +CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ @@ -243,9 +299,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 @@ -314,7 +367,7 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ((COL_ADDR_BITS - 9) << 20) | \ (BURST_LEN << 19) | \ - ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \ + ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \ ((-1) << (32 - BANK_ADDR_BITS))) #define MDMISC_WALAT(n) (((n) & 3) << 16) @@ -365,7 +418,7 @@ ivt_end: #define DCD_VERSION 0x40 #define DDR_SEL_VAL 3 /* DDR3 */ -#if PHYS_SDRAM_1_WIDTH == 16 +#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16 #define DSE1_VAL 6 /* Drive Strength for DATA lines */ #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ #else @@ -412,7 +465,9 @@ ivt_end: #define MMDC1_MDOR 0x021b0030 #define MMDC1_MDASP 0x021b0040 +#define MMDC1_MAARCR 0x021b0400 #define MMDC1_MAPSR 0x021b0404 +#define MMDC1_MADPCR0 0x021b0410 #define MMDC1_MPZQHWCTRL 0x021b0800 #define MMDC1_MPWLGCR 0x021b0808 @@ -433,7 +488,11 @@ ivt_end: #define MMDC1_MPWRDLST 0x021b0854 #define MMDC1_MPRDDLHWCTL 0x021b0860 #define MMDC1_MPWRDLHWCTL 0x021b0864 +#define MMDC1_MPDGHWST0 0x021b087c +#define MMDC1_MPDGHWST1 0x021b0880 #define MMDC1_MPPDCMPR2 0x021b0890 +#define MMDC1_MPDGHWST2 0x021b0884 +#define MMDC1_MPDGHWST3 0x021b0888 #define MMDC1_MPSWDRDR0 0x021b0898 #define MMDC1_MPSWDRDR1 0x021b089c #define MMDC1_MPSWDRDR2 0x021b08a0 @@ -444,9 +503,7 @@ ivt_end: #define MMDC1_MPSWDRDR7 0x021b08b4 #define MMDC1_MPMUR0 0x021b08b8 -#if PHYS_SDRAM_1_WIDTH == 64 -#define MMDC2_MDPDC 0x021b4004 - +#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64 #define MMDC2_MPWLGCR 0x021b4808 #define MMDC2_MPWLDECTRL0 0x021b480c #define MMDC2_MPWLDECTRL1 0x021b4810 @@ -487,7 +544,20 @@ ivt_end: #endif #ifdef CONFIG_SOC_MX6Q +#define IOMUXC_GPR0 0x020e0000 #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_GPR2 0x020e0008 +#define IOMUXC_GPR3 0x020e000c +#define IOMUXC_GPR4 0x020e0010 +#define IOMUXC_GPR5 0x020e0014 +#define IOMUXC_GPR6 0x020e0018 +#define IOMUXC_GPR7 0x020e001c +#define IOMUXC_GPR8 0x020e0020 +#define IOMUXC_GPR9 0x020e0024 +#define IOMUXC_GPR10 0x020e0028 +#define IOMUXC_GPR11 0x020e002c +#define IOMUXC_GPR12 0x020e0030 +#define IOMUXC_GPR13 0x020e0034 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 @@ -595,10 +665,8 @@ ivt_end: #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c -#define TX6_I2C1_SEL_INP_VAL 1 -#endif - -#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +#define TX6_I2C1_SEL_INP_VAL 0 +#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) #define IOMUXC_GPR1 0x020e0004 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 @@ -712,39 +780,48 @@ dcd_hdr: MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079) MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL) MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL) - - /* ENET_REF_CLK */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012) - /* ETN PHY nRST */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0) - /* ETN PHY Power */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0) - /* RESET_OUT GPIO_7_12 */ - MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0) - +#ifndef CONFIG_TX6_EMMC + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#ifndef CONFIG_TX6QP MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ - +#else + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x007236c1 */ +#endif + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ /* enable all relevant clocks... */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ - MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */ +// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */ MXC_DCD_ITEM(0x020c80b0, 0x00065b9a) MXC_DCD_ITEM(0x020c80c0, 0x000f4240) /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ +#ifdef CONFIG_TX6QP + /* enable AXI cache for VDOA/VPU/IPU */ + MXC_DCD_ITEM(IOMUXC_GPR4, 0xf00000cf) + /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ + MXC_DCD_ITEM(IOMUXC_GPR6, 0x77177717) + MXC_DCD_ITEM(IOMUXC_GPR7, 0x77177717) +#endif /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ @@ -859,8 +936,51 @@ dcd_hdr: MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK) +#endif +#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16 +#define DO_DDR_CALIB #endif /* SDRAM initialization */ +#define WL_DLY_DQS_VAL 30 +#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) + + /* ZQ calibration */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */ + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001) + + MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) + MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) + MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) + MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) +#if defined(CONFIG_SOC_MX6Q) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e) +#elif defined(CONFIG_SOC_MX6DL) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223) +#elif defined(CONFIG_SOC_MX6S) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238) +#else +#error No DGCTRL settings for selected SoC +#endif + MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ + MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ + MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ + MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ + /* MPRDDQBY[0..7]DL */ MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333) @@ -870,6 +990,9 @@ dcd_hdr: MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333) +#define MPMUR_FRC_MSR (1 << 11) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) /* MDMISC */ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002) @@ -910,7 +1033,6 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val)) MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) #endif - MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ @@ -919,8 +1041,14 @@ dcd_hdr: /* DDR3 calibration */ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ +#ifdef CONFIG_TX6QP + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(MMDC1_MAARCR, BIT(25)) /* MMDC reorder disable BOOT_CFG3[5:4] */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif MXC_DCD_ITEM(MMDC1_MAPSR, 1) +#ifdef DO_DDR_CALIB /* ZQ calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */ @@ -928,67 +1056,12 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000) - -#define WL_DLY_DQS_VAL 30 -#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0) -#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) - /* Write leveling */ - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) - MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */ - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - - MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) - MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) - MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) - MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) - -#if PHYS_SDRAM_1_WIDTH > 16 -#define DO_DDR_CALIB #endif - /* DQS gating calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ #endif - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000) - - MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ - - MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ - MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ - MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ - MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ -#define MPMUR_FRC_MSR (1 << 11) - MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) - MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) -#ifdef DO_DDR_CALIB - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) -#else /* DO_DDR_CALIB */ - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160) - MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a) - MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) - MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) -#endif /* DO_DDR_CALIB */ - MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* DRAM_SDQS[0..7] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) @@ -1007,17 +1080,13 @@ dcd_hdr: MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) -#else /* DO_DDR_CALIB */ - MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c) - MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a) -#endif /* DO_DDR_CALIB */ -#ifdef DO_DDR_CALIB + /* Write delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013) MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) -#if PHYS_SDRAM_1_WIDTH == 64 +#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ @@ -1025,11 +1094,6 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f) #endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) -#else /* DO_DDR_CALIB */ - MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f) - MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f) - MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) - MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1