X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=87ff82bb892b750f3a3cd9c14797fa064f220598;hb=b634fa6430e1b8e8477b45c8d07a1a6a56e8656d;hp=1d09de4ac675bb30f50cad15a0555780452bdef9;hpb=3d5920a31bb846249385e1ca5c086662c39bc44e;p=karo-tx-uboot.git

diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c
index 1d09de4ac6..87ff82bb89 100644
--- a/board/karo/tx6/tx6qdl.c
+++ b/board/karo/tx6/tx6qdl.c
@@ -1,17 +1,7 @@
 /*
  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:     GPL-2.0+
  *
  */
 #include <common.h>
@@ -67,68 +57,95 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MUX_CFG_SION			IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
-
-enum {
-	MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
-};
+#define MUX_CFG_SION		IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
 
 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
 #ifdef CONFIG_SECURE_BOOT
 char __csf_data[0] __attribute__((section(".__csf_data")));
 #endif
 
+#define TX6_DEFAULT_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |	\
+					     PAD_CTL_SPEED_MED |	\
+					     PAD_CTL_DSE_40ohm |	\
+					     PAD_CTL_SRE_FAST)
+#define TX6_FEC_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |	\
+					     PAD_CTL_SPEED_MED |	\
+					     PAD_CTL_DSE_40ohm |	\
+					     PAD_CTL_SRE_SLOW)
+#define TX6_GPIO_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					     PAD_CTL_SPEED_MED |	\
+					     PAD_CTL_DSE_34ohm |	\
+					     PAD_CTL_SRE_FAST)
+#define TX6_I2C_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					     PAD_CTL_HYS |		\
+					     PAD_CTL_SPEED_LOW |	\
+					     PAD_CTL_DSE_40ohm |	\
+					     PAD_CTL_SRE_SLOW)
+
 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
 	/* RESET_OUT */
-	MX6_PAD_GPIO_17__GPIO7_IO12,
+	MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
 
 	/* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-	MX6_PAD_SD3_DAT7__UART1_TX_DATA,
-	MX6_PAD_SD3_DAT6__UART1_RX_DATA,
-	MX6_PAD_SD3_DAT1__UART1_RTS_B,
-	MX6_PAD_SD3_DAT0__UART1_CTS_B,
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-	MX6_PAD_SD4_DAT4__UART2_RX_DATA,
-	MX6_PAD_SD4_DAT7__UART2_TX_DATA,
-	MX6_PAD_SD4_DAT5__UART2_RTS_B,
-	MX6_PAD_SD4_DAT6__UART2_CTS_B,
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART3_BASE
-	MX6_PAD_EIM_D24__UART3_TX_DATA,
-	MX6_PAD_EIM_D25__UART3_RX_DATA,
-	MX6_PAD_SD3_RST__UART3_RTS_B,
-	MX6_PAD_SD3_DAT3__UART3_CTS_B,
+	MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 	/* internal I2C */
-	MX6_PAD_EIM_D28__I2C1_SDA,
-	MX6_PAD_EIM_D21__I2C1_SCL,
+	MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
 
 	/* FEC PHY GPIO functions */
-	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
-	MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
-	MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
+	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
+	TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
+	MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
+	TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
+	MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
 };
 
 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 	/* FEC functions */
-	MX6_PAD_ENET_MDC__ENET_MDC,
-	MX6_PAD_ENET_MDIO__ENET_MDIO,
-	MX6_PAD_GPIO_16__ENET_REF_CLK,
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER,
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN,
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
+	MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
+	MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
+						     PAD_CTL_SPEED_LOW |
+						     PAD_CTL_DSE_80ohm |
+						     PAD_CTL_SRE_SLOW),
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
+};
+
+static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+	/* internal I2C */
+	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
+	TX6_GPIO_PAD_CTRL,
+	MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
+	TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 	/* internal I2C */
-	MX6_PAD_EIM_D28__I2C1_SDA,
-	MX6_PAD_EIM_D21__I2C1_SCL,
+	MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
+	MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
 };
 
 static const struct gpio const tx6qdl_gpios[] = {
@@ -142,13 +159,95 @@ static const struct gpio const tx6qdl_gpios[] = {
 	{ TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 };
 
-/*
- * Functions
- */
+static int pmic_addr __data;
+
+#if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
+#define SCL_BANK	(TX6_I2C1_SCL_GPIO / 32)
+#define SDA_BANK	(TX6_I2C1_SDA_GPIO / 32)
+#define SCL_BIT		(1 << (TX6_I2C1_SCL_GPIO % 32))
+#define SDA_BIT		(1 << (TX6_I2C1_SDA_GPIO % 32))
+
+static void * const gpio_ports[] = {
+	(void *)GPIO1_BASE_ADDR,
+	(void *)GPIO2_BASE_ADDR,
+	(void *)GPIO3_BASE_ADDR,
+	(void *)GPIO4_BASE_ADDR,
+	(void *)GPIO5_BASE_ADDR,
+	(void *)GPIO6_BASE_ADDR,
+	(void *)GPIO7_BASE_ADDR,
+};
+
+static void tx6_i2c_recover(void)
+{
+	int i;
+	int bad = 0;
+	struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
+	struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
+
+	if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
+	    (readl(&sda_regs->gpio_psr) & SDA_BIT))
+		return;
+
+	debug("Clearing I2C bus\n");
+	if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
+		printf("I2C SCL stuck LOW\n");
+		bad++;
+
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+						 ARRAY_SIZE(tx6_i2c_gpio_pads));
+	}
+	if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
+		printf("I2C SDA stuck LOW\n");
+
+		clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		if (!bad++)
+			imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+							 ARRAY_SIZE(tx6_i2c_gpio_pads));
+
+		udelay(10);
+
+		for (i = 0; i < 18; i++) {
+			u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
+
+			debug("%sing SCL\n",
+			      (reg & SCL_BIT) ? "Sett" : "Clear");
+			writel(reg, &scl_regs->gpio_dr);
+			udelay(5);
+			if (reg & SCL_BIT) {
+				if (readl(&sda_regs->gpio_psr) & SDA_BIT)
+					break;
+				if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
+					break;
+				break;
+			}
+		}
+	}
+	if (bad) {
+		bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
+		bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
+
+		if (scl && sda) {
+			printf("I2C bus recovery succeeded\n");
+		} else {
+			printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
+			       scl, sda);
+		}
+		imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
+						 ARRAY_SIZE(tx6_i2c_pads));
+	}
+}
+#endif
+
 /* placed in section '.data' to prevent overwriting relocation info
  * overlayed with bss
  */
-static u32 wrsr __attribute__((section(".data")));
+static u32 wrsr __data;
 
 #define WRSR_POR			(1 << 4)
 #define WRSR_TOUT			(1 << 1)
@@ -208,42 +307,95 @@ static void print_reset_cause(void)
 
 static const char __data *tx6_mod_suffix;
 
-static void tx6qdl_print_cpuinfo(void)
+#ifdef CONFIG_IMX6_THERMAL
+#include <thermal.h>
+#include <imx_thermal.h>
+#include <fuse.h>
+
+static void print_temperature(void)
+{
+	struct udevice *thermal_dev;
+	int cpu_tmp, minc, maxc, ret;
+	char const *grade_str;
+	static u32 __data thermal_calib;
+
+	puts("Temperature: ");
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_AUTOMOTIVE:
+		grade_str = "Automotive";
+		break;
+	case TEMP_INDUSTRIAL:
+		grade_str = "Industrial";
+		break;
+	case TEMP_EXTCOMMERCIAL:
+		grade_str = "Extended Commercial";
+		break;
+	default:
+		grade_str = "Commercial";
+	}
+	printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
+	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+	if (ret == 0) {
+		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+		if (ret == 0)
+			printf(" at %dC", cpu_tmp);
+		else
+			puts(" - failed to read sensor data");
+	} else {
+		puts(" - no sensor device found");
+	}
+
+	if (fuse_read(1, 6, &thermal_calib) == 0) {
+		printf(" - calibration data 0x%08x\n", thermal_calib);
+	} else {
+		puts(" - Failed to read thermal calib fuse\n");
+	}
+}
+#else
+static inline void print_temperature(void)
+{
+}
+#endif
+
+int checkboard(void)
 {
 	u32 cpurev = get_cpu_rev();
 	char *cpu_str = "?";
 
-	switch ((cpurev >> 12) & 0xff) {
-	case MXC_CPU_MX6SL:
+	if (is_cpu_type(MXC_CPU_MX6SL)) {
 		cpu_str = "SL";
 		tx6_mod_suffix = "?";
-		break;
-	case MXC_CPU_MX6DL:
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
 		cpu_str = "DL";
 		tx6_mod_suffix = "U";
-		break;
-	case MXC_CPU_MX6SOLO:
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		cpu_str = "SOLO";
 		tx6_mod_suffix = "S";
-		break;
-	case MXC_CPU_MX6Q:
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
 		cpu_str = "Q";
 		tx6_mod_suffix = "Q";
-		break;
+	} else if (is_cpu_type(MXC_CPU_MX6QP)) {
+		cpu_str = "QP";
+		tx6_mod_suffix = "QP";
 	}
 
-	printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
-		cpu_str,
-		(cpurev & 0x000F0) >> 4,
-		(cpurev & 0x0000F) >> 0,
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
+	       cpu_str,
+	       (cpurev & 0x000F0) >> 4,
+	       (cpurev & 0x0000F) >> 0,
+	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
 
+	print_temperature();
 	print_reset_cause();
 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 	check_cpu_temperature(1);
 #endif
+	tx6_i2c_recover();
+	return 0;
 }
 
+/* serial port not initialized at this point */
 int board_early_init_f(void)
 {
 	return 0;
@@ -254,155 +406,164 @@ static bool tx6_temp_check_enabled = true;
 #else
 #define tx6_temp_check_enabled	0
 #endif
-static int pmic_addr __data;
 
-#if defined(CONFIG_SOC_MX6Q)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e00a4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e00c4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e03b8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e03d8
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21	0x020e0898
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28	0x020e089c
-#define I2C1_SEL_INPUT_VAL			0
+#ifdef CONFIG_TX6_NAND
+#define TX6_FLASH_SZ	(CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#else
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ	(CONFIG_MMC_BOOT_SIZE / 4096 + 2)
+#else
+#define TX6_FLASH_SZ	2
 #endif
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e0158
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e0174
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e0528
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e0544
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21	0x020e0868
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28	0x020e086c
-#define I2C1_SEL_INPUT_VAL			1
+#endif /* CONFIG_TX6_NAND */
+
+#define TX6_DDR_SZ	(ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
+
+static char tx6_mem_table[] = {
+	'4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
+	'1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
+	'0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
+	'?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
+	'?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
+	'2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
+	'?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
+	'5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
+	'3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
+	'?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
+	'?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
+	'6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
+};
+
+#ifdef CONFIG_RN5T567
+/* PMIC settings */
+#define VDD_RTC_VAL		rn5t_mV_to_regval_rtc(3000)
+#define VDD_CORE_VAL		rn5t_mV_to_regval(1400)		/* DCDC1 */
+#define VDD_CORE_VAL_LP		rn5t_mV_to_regval(900)
+#define VDD_SOC_VAL		rn5t_mV_to_regval(1400)		/* DCDC2 */
+#define VDD_SOC_VAL_LP		rn5t_mV_to_regval(1400)
+#define VDD_DDR_VAL		rn5t_mV_to_regval(1350)		/* DCDC3 */
+#define VDD_DDR_VAL_LP		rn5t_mV_to_regval(1350)
+#define VDD_HIGH_VAL		rn5t_mV_to_regval(3000)		/* DCDC4 */
+#define VDD_HIGH_VAL_LP		rn5t_mV_to_regval(3000)
+#define VDD_IO_INT_VAL		rn5t_mV_to_regval2(3300)	/* LDO1 */
+#define VDD_IO_INT_VAL_LP	rn5t_mV_to_regval2(3300)
+#define VDD_IO_EXT_VAL		rn5t_mV_to_regval2(3300)	/* LDO2 */
+#define VDD_IO_EXT_VAL_LP	rn5t_mV_to_regval2(3300)
+
+static struct pmic_regs rn5t567_regs[] = {
+	{ RN5T567_NOETIMSET, 0x5, },
+	{ RN5T567_DC1DAC, VDD_CORE_VAL, },
+	{ RN5T567_DC2DAC, VDD_SOC_VAL, },
+	{ RN5T567_DC3DAC, VDD_DDR_VAL, },
+	{ RN5T567_DC4DAC, VDD_HIGH_VAL, },
+	{ RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
+	{ RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
+	{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
+	{ RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
+	{ RN5T567_DC1CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+	{ RN5T567_DC2CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+	{ RN5T567_DC3CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+	{ RN5T567_DC4CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+	{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
+	{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
+	{ RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
+	{ RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
+	{ RN5T567_LDOEN1, 0x03, ~0x1f, },
+	{ RN5T567_LDOEN2, 0x10, ~0x30, },
+	{ RN5T567_LDODIS, 0x1c, ~0x1f, },
+	{ RN5T567_INTPOL, 0, },
+	{ RN5T567_INTEN, 0x3, },
+	{ RN5T567_DCIREN, 0xf, },
+	{ RN5T567_EN_GPIR, 0, },
+};
 #endif
 
-#define GPIO_DR 0
-#define GPIO_DIR 4
-#define GPIO_PSR 8
-
-static const struct i2c_gpio_regs {
-	const char *label;
-	u32 gpio;
-	unsigned long gpio_base;
-	unsigned long muxctl;
-	unsigned long padctl;
-	unsigned long sel_input;
-} tx6_i2c_iomux_regs[] = {
-	{
-		.label = "PMIC SCL",
-		.gpio = TX6_I2C1_SCL_GPIO,
-		.gpio_base = GPIO3_BASE_ADDR,
-		.muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21,
-		.padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21,
-		.sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21,
-	}, {
-		.label = "PMIC SDA",
-		.gpio = TX6_I2C1_SDA_GPIO,
-		.gpio_base = GPIO3_BASE_ADDR,
-		.muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28,
-		.padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28,
-		.sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28,
-	},
+static struct {
+	uchar addr;
+	uchar rev;
+	struct pmic_regs *regs;
+	size_t num_regs;
+} tx6_mod_revs[] = {
+#ifdef CONFIG_LTC3676
+	{ 0x3c, 1, NULL, 0, },
+#endif
+#ifdef CONFIG_RN5T567
+	{ 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
+#endif
 };
 
-static inline u32 __tx6_readl(void *addr,
-			const char *fn, int ln)
+static inline char tx6_mem_suffix(void)
 {
-	u32 val = readl(addr);
-	debug("%s@%d: read %08x from %p\n", fn, ln, val, addr);
-	return val;
-}
-#undef readl
-#define readl(a)	__tx6_readl((void *)(a), __func__, __LINE__)
+	size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
 
-static inline void __tx6_writel(u32 val, void *addr,
-				const char *fn, int ln)
+	debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+	      TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+	if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+		return '?';
+	if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
+		return '7';
+	if (mem_idx == 8)
+		return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
+	return tx6_mem_table[mem_idx];
+};
+
+static int tx6_get_mod_rev(unsigned int pmic_id)
 {
-	debug("%s@%d: writing %08x to %p\n", fn, ln, val, addr);
-	writel(val, addr);
+	if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
+		return tx6_mod_revs[pmic_id].rev;
+
+	return 0;
 }
-#undef writel
-#define writel(v, a)	__tx6_writel(v, (void *)(a), __func__, __LINE__)
 
-static void tx6_i2c_recover(void)
+static int tx6_pmic_probe(void)
 {
 	int i;
-	int bad = 0;
-	int failed = 0;
-#define MAX_TRIES 100
 
-	debug("Clearing I2C bus\n");
+	debug("%s@%d: \n", __func__, __LINE__);
 
-	for (i = 0; i < ARRAY_SIZE(tx6_i2c_iomux_regs); i++) {
-		int gpio = tx6_i2c_iomux_regs[i].gpio;
-		u32 gpio_mask = 1 << (gpio % 32);
-
-		void *gpio_base = (void *)tx6_i2c_iomux_regs[i].gpio_base;
-
-		if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
-			int retries = MAX_TRIES;
-
-			bad++;
-			printf("%s (GPIO%u_%u) is not HIGH\n",
-				tx6_i2c_iomux_regs[i].label,
-				gpio / 32 + 1, gpio % 32);
-			writel(readl(gpio_base + GPIO_DR) | gpio_mask,
-				gpio_base + GPIO_DR);
-			writel(readl(gpio_base + GPIO_DIR) | gpio_mask,
-				gpio_base + GPIO_DIR);
-			writel(0x15, tx6_i2c_iomux_regs[i].muxctl);
-			writel(0x0f079, tx6_i2c_iomux_regs[i].padctl);
-			writel(I2C1_SEL_INPUT_VAL, tx6_i2c_iomux_regs[i].sel_input);
-			if ((readl(gpio_base + GPIO_DR) & gpio_mask) == 0)
-				hang();
-			if ((readl(gpio_base + GPIO_DIR) & gpio_mask) == 0)
-				hang();
-			while ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0 &&
-				retries-- > 0) {
-				udelay(100);
-			}
-			writel(readl(gpio_base + GPIO_DIR) & ~gpio_mask,
-				gpio_base + GPIO_DIR);
-
-			if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
-				printf("Failed to force %s (GPIO%u_%u) HIGH\n",
-					tx6_i2c_iomux_regs[i].label,
-					gpio / 32 + 1, gpio % 32);
-				failed++;
-			} else if (retries < MAX_TRIES) {
-				printf("%s (GPIO%u_%u) forced HIGH after %u loops\n",
-					tx6_i2c_iomux_regs[i].label,
-					gpio / 32 + 1, gpio % 32,
-					MAX_TRIES - retries);
-			}
-		} else {
-			debug("%s (GPIO%u_%u) is HIGH\n",
-				tx6_i2c_iomux_regs[i].label,
-				gpio / 32 + 1, gpio % 32);
+	for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
+		u8 i2c_addr = tx6_mod_revs[i].addr;
+		int ret = i2c_probe(i2c_addr);
+
+		if (ret == 0) {
+			debug("I2C probe succeeded for addr 0x%02x\n",
+			      i2c_addr);
+			return i;
 		}
+		debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
 	}
-	debug("Setting up I2C Pads\n");
-	imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
-					ARRAY_SIZE(tx6_i2c_pads));
-	if (bad) {
-		if (failed)
-			printf("I2C bus recovery FAILED\n");
-		else
-			printf("I2C bus recovery succeeded\n");
-	}
+	return -EINVAL;
 }
 
-#define pr_reg(b, n)	debug("%12s@%p=%08x\n", #n, (void *)(b) + (n), readl((b) + (n)))
-
-static inline void dump_regs(void)
+static int tx6_mipi(void)
 {
-	pr_reg(GPIO3_BASE_ADDR, GPIO_DR);
-	pr_reg(GPIO3_BASE_ADDR, GPIO_DIR);
-	pr_reg(GPIO3_BASE_ADDR, GPIO_PSR);
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
+	u32 gp1 = readl(&fuse->gp1);
+
+	debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
+	return gp1 & 1;
 }
 
 int board_init(void)
 {
 	int ret;
+	int pmic_id;
+
+	debug("%s@%d: \n", __func__, __LINE__);
+
+	pmic_id = tx6_pmic_probe();
+	if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
+		pmic_addr = tx6_mod_revs[pmic_id].addr;
+
+	printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+	       tx6_mod_suffix,
+	       is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
+	       tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
+	       tx6_mem_suffix());
+
+	get_hab_status();
 
 	ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 	if (ret < 0) {
@@ -425,7 +586,8 @@ int board_init(void)
 		return 0;
 	}
 
-	ret = tx6_pmic_init(pmic_addr);
+	ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
+			    tx6_mod_revs[pmic_id].num_regs);
 	if (ret) {
 		printf("Failed to setup PMIC voltages: %d\n", ret);
 		hang();
@@ -435,62 +597,66 @@ int board_init(void)
 
 int dram_init(void)
 {
+	debug("%s@%d: \n", __func__, __LINE__);
+
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
+				    PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 	return 0;
 }
 
 void dram_init_banksize(void)
 {
+	debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
+	      CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
-			PHYS_SDRAM_1_SIZE);
+					       PHYS_SDRAM_1_SIZE);
 #if CONFIG_NR_DRAM_BANKS > 1
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
-			PHYS_SDRAM_2_SIZE);
+					       PHYS_SDRAM_2_SIZE);
 #endif
 }
 
 #ifdef	CONFIG_FSL_ESDHC
-#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |		\
-	PAD_CTL_SRE_FAST)
+#define SD_PAD_CTRL		MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |	\
+					     PAD_CTL_SPEED_MED |	\
+					     PAD_CTL_DSE_40ohm |	\
+					     PAD_CTL_SRE_FAST)
 
 static const iomux_v3_cfg_t mmc0_pads[] = {
-	MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
 	/* SD1 CD */
-	MX6_PAD_SD3_CMD__GPIO7_IO02,
+	MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t mmc1_pads[] = {
-	MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
 	/* SD2 CD */
-	MX6_PAD_SD3_CLK__GPIO7_IO03,
+	MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
 };
 
 #ifdef CONFIG_TX6_EMMC
 static const iomux_v3_cfg_t mmc3_pads[] = {
-	MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
 	/* eMMC RESET */
-	MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
-						PAD_CTL_DSE_40ohm),
+	MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
 };
 #endif
 
@@ -548,9 +714,9 @@ int board_mmc_getcd(struct mmc *mmc)
 		return 1;
 
 	debug("SD card %d is %spresent (GPIO %d)\n",
-		cfg - tx6qdl_esdhc_cfg,
-		gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
-		cfg->cd_gpio);
+	      cfg - tx6qdl_esdhc_cfg,
+	      gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
+	      cfg->cd_gpio);
 	return !gpio_get_value(cfg->cd_gpio);
 }
 
@@ -558,6 +724,8 @@ int board_mmc_init(bd_t *bis)
 {
 	int i;
 
+	debug("%s@%d: \n", __func__, __LINE__);
+
 	for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 		struct mmc *mmc;
 		struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
@@ -568,10 +736,11 @@ int board_mmc_init(bd_t *bis)
 
 		if (cfg->cd_gpio >= 0) {
 			ret = gpio_request_one(cfg->cd_gpio,
-					GPIOFLAG_INPUT, "MMC CD");
+					       GPIOFLAG_INPUT, "MMC CD");
 			if (ret) {
 				printf("Error %d requesting GPIO%d_%d\n",
-					ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+				       ret, cfg->cd_gpio / 32,
+				       cfg->cd_gpio % 32);
 				continue;
 			}
 		}
@@ -591,11 +760,6 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_FEC_MXC
 
-#define FEC_PAD_CTL	(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
-			PAD_CTL_SRE_FAST)
-#define FEC_PAD_CTL2	(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
-#define GPIO_PAD_CTL	(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
 #ifndef ETH_ALEN
 #define ETH_ALEN 6
 #endif
@@ -604,11 +768,13 @@ int board_eth_init(bd_t *bis)
 {
 	int ret;
 
+	debug("%s@%d: \n", __func__, __LINE__);
+
 	/* delay at least 21ms for the PHY internal POR signal to deassert */
 	udelay(22000);
 
 	imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
-					ARRAY_SIZE(tx6qdl_fec_pads));
+					 ARRAY_SIZE(tx6qdl_fec_pads));
 
 	/* Deassert RESET to the external phy */
 	gpio_set_value(TX6_FEC_RST_GPIO, 1);
@@ -624,8 +790,8 @@ static void tx6_init_mac(void)
 {
 	u8 mac[ETH_ALEN];
 
-	imx_get_mac_from_fuse(-1, mac);
-	if (!is_valid_ether_addr(mac)) {
+	imx_get_mac_from_fuse(0, mac);
+	if (!is_valid_ethaddr(mac)) {
 		printf("No valid MAC address programmed\n");
 		return;
 	}
@@ -682,27 +848,27 @@ void show_activity(int arg)
 
 static const iomux_v3_cfg_t stk5_pads[] = {
 	/* SW controlled LED on STK5 baseboard */
-	MX6_PAD_EIM_A18__GPIO2_IO20,
+	MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
 
 	/* I2C bus on DIMM pins 40/41 */
-	MX6_PAD_GPIO_6__I2C3_SDA,
-	MX6_PAD_GPIO_3__I2C3_SCL,
+	MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
+	MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
 
 	/* TSC200x PEN IRQ */
-	MX6_PAD_EIM_D26__GPIO3_IO26,
+	MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
 
 	/* EDT-FT5x06 Polytouch panel */
-	MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
-	MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
-	MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
+	MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
+	MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
+	MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
 
 	/* USBH1 */
-	MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
-	MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
 	/* USBOTG */
-	MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
-	MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
-	MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
+	MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
+	MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
@@ -716,18 +882,15 @@ static const struct gpio stk5_gpios[] = {
 };
 
 #ifdef CONFIG_LCD
-static u16 tx6_cmap[256];
 vidinfo_t panel_info = {
 	/* set to max. size supported by SoC */
 	.vl_col = 1920,
 	.vl_row = 1080,
 
 	.vl_bpix = LCD_COLOR32,	   /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
-	.cmap = tx6_cmap,
 };
 
 static struct fb_videomode tx6_fb_modes[] = {
-#ifndef CONFIG_SYS_LVDS_IF
 	{
 		/* Standard VGA timing */
 		.name		= "VGA",
@@ -761,6 +924,24 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.lower_margin	= 10,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
+	{
+		/* Emerging ETM0700G0DH6 800 x 480 display.
+		 * 152.4 mm x 91.44 mm display area.
+		 */
+		.name		= "ET0700",
+		.refresh	= 60,
+		.xres		= 800,
+		.yres		= 480,
+		.pixclock	= KHZ2PICOS(33260),
+		.left_margin	= 88,
+		.hsync_len	= 128,
+		.right_margin	= 40,
+		.upper_margin	= 33,
+		.vsync_len	= 2,
+		.lower_margin	= 10,
+		.sync		= FB_SYNC_CLK_LAT_FALL,
+	},
+#ifndef CONFIG_SYS_LVDS_IF
 	{
 		/* Emerging ET0350G0DH6 320 x 240 display.
 		 * 70.08 mm x 52.56 mm display area.
@@ -770,10 +951,10 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.xres		= 320,
 		.yres		= 240,
 		.pixclock	= KHZ2PICOS(6500),
-		.left_margin	= 68 - 34,
+		.left_margin	= 34,
 		.hsync_len	= 34,
 		.right_margin	= 20,
-		.upper_margin	= 18 - 3,
+		.upper_margin	= 15,
 		.vsync_len	= 3,
 		.lower_margin	= 4,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
@@ -803,12 +984,12 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.xres		= 800,
 		.yres		= 480,
 		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
+		.left_margin	= 88,
 		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
+		.right_margin	= 40,
+		.upper_margin	= 33,
 		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
+		.lower_margin	= 10,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
 	{
@@ -828,40 +1009,6 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.lower_margin	= 4, /* 4.5 according to datasheet */
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
-	{
-		/* Emerging ET0700G0DH6 800 x 480 display.
-		 * 152.4 mm x 91.44 mm display area.
-		 */
-		.name		= "ET0700",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
-		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
-		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
-		.sync		= FB_SYNC_CLK_LAT_FALL,
-	},
-	{
-		/* Emerging ET070001DM6 800 x 480 display.
-		 * 152.4 mm x 91.44 mm display area.
-		 */
-		.name		= "ET070001DM6",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
-		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
-		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
-		.sync		= 0,
-	},
 #else
 	{
 		/* HannStar HSD100PXN1
@@ -920,7 +1067,7 @@ void lcd_enable(void)
 		gpio_set_value(TX6_LCD_RST_GPIO, 1);
 		udelay(300000);
 		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
-			lcd_backlight_polarity());
+			       lcd_backlight_polarity());
 	}
 }
 
@@ -937,7 +1084,7 @@ void lcd_panel_disable(void)
 	if (lcd_enabled) {
 		debug("Switching LCD off\n");
 		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
-			!lcd_backlight_polarity());
+			       !lcd_backlight_polarity());
 		gpio_set_value(TX6_LCD_RST_GPIO, 0);
 		gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 	}
@@ -945,42 +1092,42 @@ void lcd_panel_disable(void)
 
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 	/* LCD RESET */
-	MX6_PAD_EIM_D29__GPIO3_IO29,
+	MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
 	/* LCD POWER_ENABLE */
-	MX6_PAD_EIM_EB3__GPIO2_IO31,
+	MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
 	/* LCD Backlight (PWM) */
-	MX6_PAD_GPIO_1__GPIO1_IO01,
+	MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
 
 #ifndef CONFIG_SYS_LVDS_IF
 	/* Display */
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
 #endif
 };
 
@@ -1006,14 +1153,14 @@ void lcd_ctrl_init(void *lcdbase)
 
 	if (!lcd_enabled) {
 		debug("LCD disabled\n");
-		return;
+		goto disable;
 	}
 
 	if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 		debug("Disabling LCD\n");
 		lcd_enabled = 0;
 		setenv("splashimage", NULL);
-		return;
+		goto disable;
 	}
 
 	karo_fdt_move_fdt();
@@ -1022,7 +1169,7 @@ void lcd_ctrl_init(void *lcdbase)
 	if (video_mode == NULL) {
 		debug("Disabling LCD\n");
 		lcd_enabled = 0;
-		return;
+		goto disable;
 	}
 	vm = video_mode;
 	if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
@@ -1030,12 +1177,12 @@ void lcd_ctrl_init(void *lcdbase)
 		debug("Using video mode from FDT\n");
 		vm += strlen(vm);
 		if (fb_mode.xres > panel_info.vl_col ||
-			fb_mode.yres > panel_info.vl_row) {
+		    fb_mode.yres > panel_info.vl_row) {
 			printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
-				fb_mode.xres, fb_mode.yres,
-				panel_info.vl_col, panel_info.vl_row);
+			       fb_mode.xres, fb_mode.yres,
+			       panel_info.vl_col, panel_info.vl_row);
 			lcd_enabled = 0;
-			return;
+			goto disable;
 		}
 	}
 	if (p->name != NULL)
@@ -1088,7 +1235,8 @@ void lcd_ctrl_init(void *lcdbase)
 						/* fallthru */
 					default:
 						printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
-							end - vm, vm, color_depth);
+						       end - vm, vm,
+						       color_depth);
 					}
 					bpp_set = 1;
 				} else if (!refresh_set) {
@@ -1126,13 +1274,13 @@ void lcd_ctrl_init(void *lcdbase)
 			printf(" %s", p->name);
 		}
 		printf("\n");
-		return;
+		goto disable;
 	}
 	if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 		printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
-			p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+		       p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 		lcd_enabled = 0;
-		return;
+		goto disable;
 	}
 	panel_info.vl_col = p->xres;
 	panel_info.vl_row = p->yres;
@@ -1148,27 +1296,30 @@ void lcd_ctrl_init(void *lcdbase)
 		panel_info.vl_bpix = LCD_COLOR32;
 	}
 
-	p->pixclock = KHZ2PICOS(refresh *
-		(p->xres + p->left_margin + p->right_margin + p->hsync_len) *
-		(p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
-				1000);
+	if (refresh_set || p->pixclock == 0)
+		p->pixclock = KHZ2PICOS(refresh *
+					(p->xres + p->left_margin +
+					 p->right_margin + p->hsync_len) *
+					(p->yres + p->upper_margin +
+					 p->lower_margin + p->vsync_len) /
+					1000);
 	debug("Pixel clock set to %lu.%03lu MHz\n",
-		PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+	      PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 
 	if (p != &fb_mode) {
 		int ret;
 
 		debug("Creating new display-timing node from '%s'\n",
-			video_mode);
+		      video_mode);
 		ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 		if (ret)
 			printf("Failed to create new display-timing node from '%s': %d\n",
-				video_mode, ret);
+			       video_mode, ret);
 	}
 
 	gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 	imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
-					ARRAY_SIZE(stk5_lcd_pads));
+					 ARRAY_SIZE(stk5_lcd_pads));
 
 	lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
 	switch (lcd_bus_width) {
@@ -1189,8 +1340,8 @@ void lcd_ctrl_init(void *lcdbase)
 	default:
 		lcd_enabled = 0;
 		printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
-			lcd_bus_width);
-		return;
+		       lcd_bus_width);
+		goto disable;
 	}
 	if (is_lvds()) {
 		int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
@@ -1201,7 +1352,7 @@ void lcd_ctrl_init(void *lcdbase)
 		if (lvds_chan_mask == 0) {
 			printf("No LVDS channel active\n");
 			lcd_enabled = 0;
-			return;
+			goto disable;
 		}
 
 		gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
@@ -1209,7 +1360,8 @@ void lcd_ctrl_init(void *lcdbase)
 			gpr2 |= (1 << 5) | (1 << 7);
 		gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
 		gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
-		debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+		debug("writing %08x to GPR2[%08x]\n", gpr2,
+		      IOMUXC_BASE_ADDR + 8);
 		writel(gpr2, IOMUXC_BASE_ADDR + 8);
 
 		gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
@@ -1221,8 +1373,8 @@ void lcd_ctrl_init(void *lcdbase)
 
 		debug("Initializing LCD controller\n");
 		ret = ipuv3_fb_init(p, 0, pix_fmt,
-				is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
-				di_clk_rate, -1);
+				    is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
+				    di_clk_rate, -1);
 		if (ret) {
 			printf("Failed to initialize FB driver: %d\n", ret);
 			lcd_enabled = 0;
@@ -1230,6 +1382,12 @@ void lcd_ctrl_init(void *lcdbase)
 	} else {
 		debug("Skipping initialization of LCD controller\n");
 	}
+	return;
+
+ disable:
+	lcd_enabled = 0;
+	panel_info.vl_col = 0;
+	panel_info.vl_row = 0;
 }
 #else
 #define lcd_enabled 0
@@ -1259,13 +1417,14 @@ static void stk5v5_board_init(void)
 	stk5_board_init();
 
 	ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
-			"Flexcan Transceiver");
+			       "Flexcan Transceiver");
 	if (ret) {
 		printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
 		return;
 	}
 
-	imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
+	imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
+			       TX6_GPIO_PAD_CTRL);
 }
 
 static void tx6qdl_set_cpu_clock(void)
@@ -1277,13 +1436,13 @@ static void tx6qdl_set_cpu_clock(void)
 
 	if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 		printf("%s detected; skipping cpu clock change\n",
-			(wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+		       (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
 		return;
 	}
 	if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
 		cpu_clk = mxc_get_clock(MXC_ARM_CLK);
 		printf("CPU clock set to %lu.%03lu MHz\n",
-			cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+		       cpu_clk / 1000000, cpu_clk / 1000 % 1000);
 	} else {
 		printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 	}
@@ -1291,15 +1450,9 @@ static void tx6qdl_set_cpu_clock(void)
 
 int board_late_init(void)
 {
-	int ret = 0;
 	const char *baseboard;
-#if 1
-	/* override secure_boot fuse */
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
 
-	writel(0x12, &fuse->cfg5);
-#endif
+	debug("%s@%d: \n", __func__, __LINE__);
 
 	env_cleanup();
 
@@ -1323,25 +1476,26 @@ int board_late_init(void)
 
 	if (strncmp(baseboard, "stk5", 4) == 0) {
 		if ((strlen(baseboard) == 4) ||
-			strcmp(baseboard, "stk5-v3") == 0) {
+		    strcmp(baseboard, "stk5-v3") == 0) {
 			stk5v3_board_init();
 		} else if (strcmp(baseboard, "stk5-v5") == 0) {
 			const char *otg_mode = getenv("otg_mode");
 
 			if (otg_mode && strcmp(otg_mode, "host") == 0) {
 				printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
-					otg_mode, baseboard);
+				       otg_mode, baseboard);
 				setenv("otg_mode", "none");
 			}
 			stk5v5_board_init();
 		} else {
 			printf("WARNING: Unsupported STK5 board rev.: %s\n",
-				baseboard + 4);
+			       baseboard + 4);
 		}
 	} else {
 		printf("WARNING: Unsupported baseboard: '%s'\n",
-			baseboard);
-		ret = -EINVAL;
+		       baseboard);
+		if (!had_ctrlc())
+			return -EINVAL;
 	}
 
 exit:
@@ -1349,106 +1503,6 @@ exit:
 
 	gpio_set_value(TX6_RESET_OUT_GPIO, 1);
 	clear_ctrlc();
-	return ret;
-}
-
-#ifdef CONFIG_TX6_NAND
-#define TX6_FLASH_SZ	(CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
-#else
-#ifdef CONFIG_MMC_BOOT_SIZE
-#define TX6_FLASH_SZ	(CONFIG_MMC_BOOT_SIZE / 4096 + 2)
-#else
-#define TX6_FLASH_SZ	2
-#endif
-#endif /* CONFIG_TX6_NAND */
-
-#define TX6_DDR_SZ	(ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
-
-static char tx6_mem_table[] = {
-	'4', /* 256MiB SDRAM 16bit; 128MiB NAND */
-	'1', /* 512MiB SDRAM 32bit; 128MiB NAND */
-	'0', /* 1GiB SDRAM 64bit; 128MiB NAND */
-	'?', /* 256MiB SDRAM 16bit; 256MiB NAND */
-	'?', /* 512MiB SDRAM 32bit; 256MiB NAND */
-	'2', /* 1GiB SDRAM 64bit; 256MiB NAND */
-	'?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
-	'5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
-	'3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
-	'?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
-	'?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
-	'0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
-};
-
-static inline char tx6_mem_suffix(void)
-{
-	size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
-
-	debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
-		TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
-
-	if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
-		return '?';
-
-	return tx6_mem_table[mem_idx];
-};
-
-static struct {
-	uchar addr;
-	uchar rev;
-} tx6_mod_revs[] = {
-	{ 0x3c, 1, },
-	{ 0x32, 2, },
-	{ 0x33, 3, },
-};
-
-static int tx6_get_mod_rev(unsigned int pmic_id)
-{
-	if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
-		return tx6_mod_revs[pmic_id].rev;
-
-	return 0;
-}
-
-static int tx6_pmic_probe(void)
-{
-	int i;
-
-	tx6_i2c_recover();
-	i2c_init_all();
-
-	for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
-		u8 i2c_addr = tx6_mod_revs[i].addr;
-		int ret = i2c_probe(i2c_addr);
-
-		if (ret == 0) {
-			debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
-			return i;
-		}
-		debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
-	}
-	return -EINVAL;
-}
-
-int checkboard(void)
-{
-	u32 cpurev = get_cpu_rev();
-	int cpu_variant = (cpurev >> 12) & 0xff;
-	int pmic_id;
-
-	tx6qdl_print_cpuinfo();
-
-	pmic_id = tx6_pmic_probe();
-	if (pmic_id >= 0)
-		pmic_addr = tx6_mod_revs[pmic_id].addr;
-
-	printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
-		tx6_mod_suffix,
-		cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-		is_lvds(), tx6_get_mod_rev(pmic_id),
-		tx6_mem_suffix());
-
-	get_hab_status();
-
 	return 0;
 }
 
@@ -1496,15 +1550,18 @@ int ft_board_setup(void *blob, bd_t *bd)
 		karo_fdt_enable_node(blob, "stk5led", 0);
 
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-	fdt_fixup_ethernet(blob);
 
 	karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
-				ARRAY_SIZE(tx6_touchpanels));
+				  ARRAY_SIZE(tx6_touchpanels));
 	karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
 	karo_fdt_fixup_flexcan(blob, stk5_v5);
 
-	karo_fdt_update_fb_mode(blob, video_mode);
-
+#ifdef CONFIG_SYS_LVDS_IF
+	karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
+	karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
+#else
+	karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
+#endif
 	return 0;
 }
 #endif /* CONFIG_OF_BOARD_SETUP */