X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=board%2Fmx1fs2%2Flowlevel_init.S;h=56a4819b0891478e0699dd32df04dd69c0fd63e7;hb=40b161f6aea54104d0a5e477ff6a22338e8a7b4b;hp=8211beb3f88a37c167b352fd759775a89845ab4e;hpb=8ad96012cd9e46b355ec63eb5a0155c92d8ca52c;p=karo-tx-uboot.git

diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S
index 8211beb3f8..56a4819b08 100755
--- a/board/mx1fs2/lowlevel_init.S
+++ b/board/mx1fs2/lowlevel_init.S
@@ -29,19 +29,19 @@ lowlevel_init:
 
 /* Change PERCLK1DIV to 14 ie 14+1 */
 	ldr		r0,	=PCDR
-	ldr		r1,	=CFG_PCDR_VAL
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
 	str		r1,   [r0]
 
 /* set MCU PLL Control Register 0 */
 
 	ldr		r0,	=MPCTL0
-	ldr		r1,	=CFG_MPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
 	str		r1,   [r0]
 
 /* set MCU PLL Control Register 1 */
 
 	ldr		r0,	=MPCTL1
-	ldr		r1,	=CFG_MPCTL1_VAL
+	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
 	str		r1,   [r0]
 
 /* set mpll restart bit */
@@ -63,13 +63,13 @@ lowlevel_init:
 /* set System PLL Control Register 0 */
 
 	ldr		r0,	=SPCTL0
-	ldr		r1,	=CFG_SPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
 	str		r1,   [r0]
 
 /* set System PLL Control Register 1 */
 
 	ldr		r0,	=SPCTL1
-	ldr		r1,	=CFG_SPCTL1_VAL
+	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
 	str		r1,   [r0]
 
 /* set spll restart bit */
@@ -89,11 +89,11 @@ lowlevel_init:
 	bne		1b
 
 	ldr		r0,   =CSCR
-	ldr		r1,   =CFG_CSCR_VAL
+	ldr		r1,   =CONFIG_SYS_CSCR_VAL
 	str		r1,   [r0]
 
 	ldr		r0,   =GPCR
-	ldr		r1,   =CFG_GPCR_VAL
+	ldr		r1,   =CONFIG_SYS_GPCR_VAL
 	str		r1,   [r0]
 
 /*
@@ -122,43 +122,43 @@ lowlevel_init:
 	MCR p15,0,r0,c1,c0,0
 
 	ldr		r0,	=GIUS(0)
-	ldr		r1,	=CFG_GIUS_A_VAL
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=FMCR
-	ldr		r1,	=CFG_FMCR_VAL
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0U
-	ldr		r1,	=CFG_CS0U_VAL
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0L
-	ldr		r1,	=CFG_CS0L_VAL
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1U
-	ldr		r1,	=CFG_CS1U_VAL
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1L
-	ldr		r1,	=CFG_CS1L_VAL
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4U
-	ldr		r1,	=CFG_CS4U_VAL
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4L
-	ldr		r1,	=CFG_CS4L_VAL
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5U
-	ldr		r1,	=CFG_CS5U_VAL
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5L
-	ldr		r1,	=CFG_CS5L_VAL
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
 	str		r1,   [r0]
 
 /* SDRAM Setup */
@@ -166,22 +166,22 @@ lowlevel_init:
 	ldr  r1,=0x00221000   /* adr of SDCTRL0			*/
 	ldr  r0,=0x92120200
 	str  r0,[r1,#0]       /* put in precharge command mode    */
-	ldr  r2,=0x08200000   /* adr for precharge cmd 	   */
+	ldr  r2,=0x08200000   /* adr for precharge cmd	   */
 	ldr  r0,[r2,#0]       /* precharge			   */
 	ldr  r0,=0xA2120200
 	ldr  r2,=0x08000000   /* start of SDRAM		   */
 	str  r0,[r1,#0]       /* put in auto-refresh mode	   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
 	ldr  r0,=0xB2120200
 	ldr  r2,=0x08111800
 	str  r0,[r1,#0]       /* setup for mode register of SDRAM */
-	ldr  r0,[r2,#0]       /* program mode register 	   */
+	ldr  r0,[r2,#0]       /* program mode register	   */
 	ldr  r0,=0x82124267
 	str  r0,[r1,#0]       /* back to normal operation	   */