X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=doc%2FREADME.x86;h=3bab5cf64e62902240a705e32aa3290205cd596f;hb=a665b051b5a191c2b5c1c8ed238ccf7d29b7109b;hp=af2459c7ed6af55d989f2902bbf8ec4646975aaa;hpb=1a2728ae4faf12874173de156b8a7e66cfbbeae5;p=karo-tx-uboot.git diff --git a/doc/README.x86 b/doc/README.x86 index af2459c7ed..3bab5cf64e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -18,15 +18,16 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link work with minimal adjustments on other x86 boards since coreboot deals with most of the low-level details. -U-Boot also supports booting directly from x86 reset vector without coreboot, -aka raw support or bare support. Currently Link, QEMU x86 targets and all -Intel boards support running U-Boot 'bare metal'. +U-Boot also supports booting directly from x86 reset vector, without coreboot. +In this case, known as bare mode, from the fact that it runs on the +'bare metal', U-Boot acts like a BIOS replacement. Currently Link, QEMU x86 +targets and all Intel boards support running U-Boot 'bare metal'. As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit Linux kernel as part of a FIT image. It also supports a compressed zImage. -Build Instructions ------------------- +Build Instructions for U-Boot as coreboot payload +------------------------------------------------- Building U-Boot as a coreboot payload is just like building U-Boot for targets on other architectures, like below: @@ -48,6 +49,8 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. +Build Instructions for U-Boot as BIOS replacement (bare mode) +------------------------------------------------------------- Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is @@ -58,7 +61,9 @@ $ export BUILD_ROM=y This tells the Makefile to build u-boot.rom as a target. -Link-specific instructions: +--- + +Chromebook Link specific instructions for bare mode: First, you need the following binary blobs: @@ -87,7 +92,9 @@ Now you can build U-Boot and obtain u-boot.rom: $ make chromebook_link_defconfig $ make all -Intel Crown Bay specific instructions: +--- + +Intel Crown Bay specific instructions for bare mode: U-Boot support of Intel Crown Bay board [4] relies on a binary blob called Firmware Support Package [5] to perform all the necessary initialization steps @@ -122,7 +129,9 @@ Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all -Intel Minnowboard Max instructions: +--- + +Intel Minnowboard Max instructions for bare mode: This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at @@ -188,8 +197,9 @@ Offset Description Controlling config Overall ROM image size is controlled by CONFIG_ROM_SIZE. +--- -Intel Galileo instructions: +Intel Galileo instructions for bare mode: Only one binary blob is needed for Remote Management Unit (RMU) within Intel Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is @@ -235,10 +245,10 @@ this capability yet. The command is as follows: # in the coreboot root directory $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ - -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 + -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000 -Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the -symbol address of _start (in arch/x86/cpu/start.S). +Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address +of _x86boot_start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. @@ -252,8 +262,8 @@ At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. -Test with QEMU --------------- +Test with QEMU for bare mode +---------------------------- QEMU is a fancy emulator that can enable us to test U-Boot without access to a real x86 board. Please make sure your QEMU version is 2.3.0 or above test U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows: @@ -644,13 +654,13 @@ Use the device tree for configuration where possible. For the microcode you can create a suitable device tree file using the microcode tool: - ./tools/microcode-tool -d microcode.dat create + ./tools/microcode-tool -d microcode.dat -m create or if you only have header files and not the full Intel microcode.dat database: ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ - create all + -m all create These are written to arch/x86/dts/microcode/ by default. @@ -708,6 +718,21 @@ allocation and assignment will be done by U-Boot automatically. Now you can enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC. +This script might be useful. If you feed it the output of 'pci long' from +U-Boot then it will generate a device tree fragment with the interrupt +configuration for each device (note it needs gawk 4.0.0): + + $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \ + /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \ + {patsplit(device, bdf, "[0-9a-f]+"); \ + printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \ + strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}' + +Example output: + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA +... + TODO List --------- - Audio