X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=doc%2FREADME.x86;h=c19f4a03ba07d1ddc93e182d16cf2607ec7bca3b;hb=88a0739d9d909f72fce1037ed0be95f4b62fe448;hp=a9105f87c0fc1b5933e51c8a9470d01922fcdef3;hpb=c2a4db2b8735e9bbaa0deb0c12bcbd64cfc4edc3;p=karo-tx-uboot.git diff --git a/doc/README.x86 b/doc/README.x86 index a9105f87c0..c19f4a03ba 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -14,15 +14,16 @@ including supported boards, build instructions, todo list, etc. Status ------ U-Boot supports running as a coreboot [1] payload on x86. So far only Link -(Chromebook Pixel) has been tested, but it should work with minimal adjustments -on other x86 boards since coreboot deals with most of the low-level details. +(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should +work with minimal adjustments on other x86 boards since coreboot deals with +most of the low-level details. U-Boot also supports booting directly from x86 reset vector without coreboot, -aka raw support or bare support. Currently Link and Intel Crown Bay board -support running U-Boot 'bare metal'. +aka raw support or bare support. Currently Link, QEMU x86 targets and all +Intel boards support running U-Boot 'bare metal'. -As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux -kernel as part of a FIT image. It also supports a compressed zImage. +As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit +Linux kernel as part of a FIT image. It also supports a compressed zImage. Build Instructions ------------------ @@ -32,22 +33,22 @@ on other architectures, like below: $ make coreboot-x86_defconfig $ make all -Note this default configuration will build a U-Boot payload for the Link board. +Note this default configuration will build a U-Boot payload for the QEMU board. To build a coreboot payload against another board, you can change the build configuration during the 'make menuconfig' process. x86 architecture ---> ... - (chromebook_link) Board configuration file - (chromebook_link) Board Device Tree Source (dts) file - (0x19200000) Board specific Cache-As-RAM (CAR) address + (qemu-x86) Board configuration file + (qemu-x86_i440fx) Board Device Tree Source (dts) file + (0x01920000) Board specific Cache-As-RAM (CAR) address (0x4000) Board specific Cache-As-RAM (CAR) size Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. -Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a +Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it @@ -75,10 +76,10 @@ Find the following files: * ./mainboard/google/link/descriptor.bin * ./mainboard/google/link/me.bin -* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin +* ./northbridge/intel/sandybridge/systemagent-r6.bin The 3rd one should be renamed to mrc.bin. -As for the video ROM, you can get it here [2]. +As for the video ROM, you can get it here [3]. Make sure all these binary blobs are put in the board directory. Now you can build U-Boot and obtain u-boot.rom: @@ -88,8 +89,8 @@ $ make all Intel Crown Bay specific instructions: -U-Boot support of Intel Crown Bay board [3] relies on a binary blob called -Firmware Support Package [4] to perform all the necessary initialization steps +U-Boot support of Intel Crown Bay board [4] relies on a binary blob called +Firmware Support Package [5] to perform all the necessary initialization steps as documented in the BIOS Writer Guide, including initialization of the CPU, memory controller, chipset and certain bus interfaces. @@ -105,11 +106,94 @@ in this FSP package too. Rename the first one to fsp.bin and second one to cmc.bin and put them in the board directory. +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all +Intel Minnowboard Max instructions: + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the board directory: +board/intel/minnowmax/fsp.bin + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +directory: board/intel/minnowmax/vga.bin + +You still need two more binary blobs. The first comes from the original +firmware image available from: + +http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example: + + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Then do the same with the sample SPI image provided in the FSP (SPI.bin at +the time of writing) to obtain the last image. Note that this will also +produce a flash descriptor file, but it does not seem to work, probably +because it is not designed for the Minnowmax. That is why you need to get +the flash descriptor from the original firmware as above. + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin + +Now you can build U-Boot and obtain u-boot.rom + +$ make minnowmax_defconfig +$ make all + +Intel Galileo instructions: + +Only one binary blob is needed for Remote Management Unit (RMU) within Intel +Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is +needed by the Quark SoC itself. + +You can get the binary blob from Quark Board Support Package from Intel website: + +* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin + +Rename the file and put it to the board directory by: + + $ cp RMU.bin board/intel/galileo/rmu.bin + +Now you can build U-Boot and obtain u-boot.rom + +$ make galileo_defconfig +$ make all + +QEMU x86 target instructions: + +To build u-boot.rom for QEMU x86 targets, just simply run + +$ make qemu-x86_defconfig +$ make all + +Note this default configuration will build a U-Boot for the QEMU x86 i440FX +board. To build a U-Boot against QEMU x86 Q35 board, you can change the build +configuration during the 'make menuconfig' process like below: + +Device Tree Control ---> + ... + (qemu-x86_q35) Default Device Tree for DT control + Test with coreboot ------------------ For testing U-Boot as the coreboot payload, there are things that need be paid @@ -130,9 +214,47 @@ symbol address of _start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. +To enable video you must enable these options in coreboot: + + - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) + - Keep VESA framebuffer + +At present it seems that for Minnowboard Max, coreboot does not pass through +the video information correctly (it always says the resolution is 0x0). This +works correctly for link though. + +Test with QEMU +-------------- +QEMU is a fancy emulator that can enable us to test U-Boot without access to +a real x86 board. Please make sure your QEMU version is 2.3.0 or above test +U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows: + +$ qemu-system-i386 -nographic -bios path/to/u-boot.rom + +This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU +also supports emulating an x86 board with Q35 and ICH9 based chipset, which is +also supported by U-Boot. To instantiate such a machine, call QEMU with: + +$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35 + +Note by default QEMU instantiated boards only have 128 MiB system memory. But +it is enough to have U-Boot boot and function correctly. You can increase the +system memory by pass '-m' parameter to QEMU if you want more memory: + +$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 + +This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only +supports 3 GiB maximum system memory and reserves the last 1 GiB address space +for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m' +would be 3072. + +QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will +show QEMU's VGA console window. Note this will disable QEMU's serial output. +If you want to check both consoles, use '-serial stdio'. + CPU Microcode ------------- -Modern CPUs usually require a special bit stream called microcode [5] to be +Modern CPUs usually require a special bit stream called microcode [6] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. @@ -149,7 +271,6 @@ arch/x86/dts/ for these device tree source files. Useful Commands --------------- - In keeping with the U-Boot philosophy of providing functions to check and adjust internal settings, there are several x86-specific commands that may be useful: @@ -166,7 +287,6 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to Development Flow ---------------- - These notes are for those who want to port U-Boot to a new x86 platform. Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. @@ -237,7 +357,8 @@ TODO List References ---------- [1] http://www.coreboot.org -[2] http://www.coreboot.org/~stepan/pci8086,0166.rom -[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html -[4] http://www.intel.com/fsp -[5] http://en.wikipedia.org/wiki/Microcode +[2] http://www.qemu.org +[3] http://www.coreboot.org/~stepan/pci8086,0166.rom +[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[5] http://www.intel.com/fsp +[6] http://en.wikipedia.org/wiki/Microcode