X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=drivers%2Fnet%2Fsh_eth.h;h=27fde05bd6050f8aee5f99b5869a03b9980d594f;hb=34e210f5bd9c000cec39b45483be6df52e2b6e07;hp=dd6a4224e11377ae1245fce280c9b1933cc0101d;hpb=9294fd60ae273cc7a2759a48a081a5cc655ddf23;p=karo-tx-uboot.git

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index dd6a4224e1..27fde05bd6 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,8 +1,8 @@
 /*
  * sh_eth.h - Driver for Renesas SuperH ethernet controler.
  *
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008, 2011 Renesas Solutions Corp.
+ * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -162,6 +162,32 @@ struct sh_eth_dev {
 #define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
 #define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
 #define RTRATE(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
+
+#elif defined(CONFIG_CPU_SH7724)
+#define BASE_IO_ADDR	0xA4600000
+
+#define TDLAR(port)		(BASE_IO_ADDR + 0x0018)
+#define RDLAR(port)		(BASE_IO_ADDR + 0x0020)
+
+#define EDMR(port)		(BASE_IO_ADDR + 0x0000)
+#define EDTRR(port)		(BASE_IO_ADDR + 0x0008)
+#define EDRRR(port)		(BASE_IO_ADDR + 0x0010)
+#define EESR(port)		(BASE_IO_ADDR + 0x0028)
+#define EESIPR(port)	(BASE_IO_ADDR + 0x0030)
+#define TRSCER(port)	(BASE_IO_ADDR + 0x0038)
+#define TFTR(port)		(BASE_IO_ADDR + 0x0048)
+#define FDR(port)		(BASE_IO_ADDR + 0x0050)
+#define RMCR(port)		(BASE_IO_ADDR + 0x0058)
+#define FCFTR(port)		(BASE_IO_ADDR + 0x0070)
+#define ECMR(port)		(BASE_IO_ADDR + 0x0100)
+#define RFLR(port)		(BASE_IO_ADDR + 0x0108)
+#define ECSIPR(port)	(BASE_IO_ADDR + 0x0118)
+#define PIR(port)		(BASE_IO_ADDR + 0x0120)
+#define APR(port)		(BASE_IO_ADDR + 0x0154)
+#define MPR(port)		(BASE_IO_ADDR + 0x0158)
+#define TPAUSER(port)	(BASE_IO_ADDR + 0x0164)
+#define MAHR(port)		(BASE_IO_ADDR + 0x01c0)
+#define MALR(port)		(BASE_IO_ADDR + 0x01c8)
 #endif
 
 /*
@@ -183,7 +209,7 @@ enum DMAC_M_BIT {
 	EDMR_SRST	= 0x03,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#elif defined CONFIG_CPU_SH7757
+#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
 	EDMR_SRST	= 0x01,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
@@ -325,7 +351,8 @@ enum FCFTR_BIT {
 
 /* Transfer descriptor bit */
 enum TD_STS_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
+		|| defined(CONFIG_CPU_SH7724)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -350,6 +377,10 @@ enum FELIC_MODE_BIT {
 	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 	ECMR_PRM = 0x00000001,
+#ifdef CONFIG_CPU_SH7724
+	ECMR_RTM = 0x00000010,
+#endif
+
 };
 
 #ifdef CONFIG_CPU_SH7763
@@ -357,6 +388,8 @@ enum FELIC_MODE_BIT {
 						ECMR_TXF | ECMR_MCT)
 #elif CONFIG_CPU_SH7757
 #define ECMR_CHG_DM	(ECMR_ZPF)
+#elif CONFIG_CPU_SH7724
+#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 #else
 #define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 #endif
@@ -435,4 +468,3 @@ enum RPADIR_BIT {
 enum FIFO_SIZE_BIT {
 	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 };
-