X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=drivers%2Fphy%2Fmarvell%2Fcomphy_hpipe.h;h=179e910a0c86b803868c60bc65ec7c22ac0afec5;hb=c0132f60059d4a6809341d54f2fe744db8790421;hp=0c9b5007434ba8354376480c11140893c4e6d623;hpb=01e62c7f11eb4c1fe814f109ecb34e1a176eb33b;p=karo-tx-uboot.git

diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
index 0c9b500743..179e910a0c 100644
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -78,6 +78,14 @@
 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK	\
 	(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
 
+#define HPIPE_CAL_REG1_REG			0xc
+#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET	10
+#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK		\
+	(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET	15
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK	\
+	(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
+
 #define HPIPE_SQUELCH_FFE_SETTING_REG           0x018
 
 #define HPIPE_DFE_REG0				0x01C
@@ -94,6 +102,9 @@
 	(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
 
 #define HPIPE_G1_SET_0_REG			0x034
+#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET		1
+#define HPIPE_G1_SET_0_G1_TX_AMP_MASK		\
+	(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET	7
 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK		\
 	(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
@@ -145,6 +156,14 @@
 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK		\
 	(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
 
+#define HPIPE_G1_SET_2_REG			0xf4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET	0
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK		\
+	(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET	4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK	\
+	(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
+
 #define HPIPE_VTHIMPCAL_CTRL_REG                0x104
 
 #define HPIPE_PCIE_REG0                         0x120
@@ -164,6 +183,9 @@
 #define HPIPE_MISC_CLK100M_125M_OFFSET		4
 #define HPIPE_MISC_CLK100M_125M_MASK		\
 	(0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
+#define HPIPE_MISC_ICP_FORCE_OFFSET		5
+#define HPIPE_MISC_ICP_FORCE_MASK		\
+	(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
 #define HPIPE_MISC_TXDCLK_2X_OFFSET		6
 #define HPIPE_MISC_TXDCLK_2X_MASK		\
 	(0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
@@ -197,6 +219,14 @@
 #define HPIPE_SMAPLER_MASK			\
 	(0x1 << HPIPE_SMAPLER_OFFSET)
 
+#define HPIPE_TX_REG1_REG			0x174
+#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET	5
+#define HPIPE_TX_REG1_TX_EMPH_RES_MASK		\
+	(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
+#define HPIPE_TX_REG1_SLC_EN_OFFSET		10
+#define HPIPE_TX_REG1_SLC_EN_MASK		\
+	(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
+
 #define HPIPE_PWR_CTR_DTL_REG			0x184
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET	2
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK		\
@@ -262,6 +292,9 @@
 	(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
 
 #define HPIPE_G1_SETTINGS_3_REG			0x440
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET	9
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK	\
+	(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
 
 #define HPIPE_G1_SETTINGS_4_REG			0x444
 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET	8
@@ -289,6 +322,11 @@
 #define HPIPE_DFE_CTRL_28_PIPE4_MASK		\
 	(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
 
+#define HPIPE_G1_SETTING_5_REG			0x538
+#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET	0
+#define HPIPE_G1_SETTING_5_G1_ICP_MASK		\
+	(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
+
 #define HPIPE_LANE_CONFIG0_REG			0x600
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET	0
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK	\