X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=include%2Fahci.h;h=2cc8039c3bde4dd9fa24dd3fa51974ab55e9593f;hb=74952f399b39ca4c3f999cf8d2bc43923ba0c182;hp=1940eea630e94769914964e5ba652c7d5c2669c4;hpb=8ec346e17b5bf6897f038b8ecc3ecd073e097a22;p=karo-tx-uboot.git

diff --git a/include/ahci.h b/include/ahci.h
index 1940eea630..2cc8039c3b 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -1,7 +1,4 @@
 /*
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- * Terry Lv <r65388@freescale.com>
- *
  * Copyright (C) Freescale Semiconductor, Inc. 2006.
  * Author: Jason Jin<Jason.jin@freescale.com>
  *         Zhang Wei<wei.zhang@freescale.com>
@@ -15,7 +12,6 @@
 
 #define AHCI_PCI_BAR		0x24
 #define AHCI_MAX_SG		56 /* hardware max is 64K */
-#define AHCI_MAX_CMD_SLOT	32
 #define AHCI_CMD_SLOT_SZ	32
 #define AHCI_MAX_CMD_SLOT	32
 #define AHCI_RX_FIS_SZ		256
@@ -62,6 +58,10 @@
 #define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
 #define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
 
+#ifdef CONFIG_SUNXI_AHCI
+#define PORT_P0DMACR		0x70 /* SUNXI specific "DMA register" */
+#endif
+
 /* PORT_IRQ_{STAT,MASK} bits */
 #define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
 #define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
@@ -91,6 +91,11 @@
 				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
 				| PORT_IRQ_D2H_REG_FIS
 
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK	0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
 /* PORT_CMD bits */
 #define PORT_CMD_ATAPI		(1 << 24) /* Device is ATAPI */
 #define PORT_CMD_LIST_ON	(1 << 15) /* cmd list DMA engine running */
@@ -107,29 +112,6 @@
 
 #define AHCI_MAX_PORTS		32
 
-/* SETFEATURES stuff */
-#define SETFEATURES_XFER	0x03
-#define XFER_UDMA_7		0x47
-#define XFER_UDMA_6		0x46
-#define XFER_UDMA_5		0x45
-#define XFER_UDMA_4		0x44
-#define XFER_UDMA_3		0x43
-#define XFER_UDMA_2		0x42
-#define XFER_UDMA_1		0x41
-#define XFER_UDMA_0		0x40
-#define XFER_MW_DMA_2		0x22
-#define XFER_MW_DMA_1		0x21
-#define XFER_MW_DMA_0		0x20
-#define XFER_SW_DMA_2		0x12
-#define XFER_SW_DMA_1		0x11
-#define XFER_SW_DMA_0		0x10
-#define XFER_PIO_4		0x0C
-#define XFER_PIO_3		0x0B
-#define XFER_PIO_2		0x0A
-#define XFER_PIO_1		0x09
-#define XFER_PIO_0		0x08
-#define XFER_PIO_SLOW		0x00
-
 #define ATA_FLAG_SATA		(1 << 3)
 #define ATA_FLAG_NO_LEGACY	(1 << 4) /* no legacy mode check */
 #define ATA_FLAG_MMIO		(1 << 6) /* use MMIO, not PIO */
@@ -153,12 +135,12 @@ struct ahci_sg {
 };
 
 struct ahci_ioports {
-	u32	cmd_addr;
-	u32	scr_addr;
-	u32	port_mmio;
+	void __iomem	*cmd_addr;
+	void __iomem	*scr_addr;
+	void __iomem	*port_mmio;
 	struct ahci_cmd_hdr	*cmd_slot;
 	struct ahci_sg		*cmd_tbl_sg;
-	u32	cmd_tbl;
+	ulong	cmd_tbl;
 	u32	rx_fis;
 };
 
@@ -169,8 +151,8 @@ struct ahci_probe_ent {
 	u32	hard_port_no;
 	u32	host_flags;
 	u32	host_set_flags;
-	u32	mmio_base;
-	u32	pio_mask;
+	void __iomem *mmio_base;
+	u32     pio_mask;
 	u32	udma_mask;
 	u32	flags;
 	u32	cap;	/* cache of HOST_CAP register */
@@ -178,6 +160,7 @@ struct ahci_probe_ent {
 	u32	link_port_map; /*linkup port map*/
 };
 
-int ahci_init(u32 base);
+int ahci_init(void __iomem *base);
+int ahci_reset(void __iomem *base);
 
 #endif