X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fio.h;h=1213fe2ab534cedce1e8eb912b628be11b8ea6a5;hb=f8008f144b01b6b2f64ccac00dc3f1131687c74e;hp=a66c7043611ed987c09f736f86332830e5cf7a78;hpb=73bb4c72407aca3c2f461708bb872a23f2b1bf5a;p=karo-tx-uboot.git

diff --git a/include/configs/io.h b/include/configs/io.h
index a66c704361..1213fe2ab5 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -2,30 +2,13 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_IO	        1	/*  on a Io board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -34,11 +17,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		io
-#define CONFIG_IDENT_STRING	" io 0.04"
+#define CONFIG_IDENT_STRING	" io 0.06"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
-#define CONFIG_LAST_STAGE_INIT		/* call last_stage_init */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
@@ -48,9 +33,10 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
 
@@ -75,8 +61,12 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -107,7 +97,7 @@
 /*
  * I2C stuff
  */
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
 
 /* Temp sensor/hwmon/dtt */
 #define CONFIG_DTT_LM63		1	/* National LM63	*/
@@ -132,7 +122,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
@@ -209,9 +198,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -229,13 +217,20 @@
 #define CONFIG_SYS_EBC_PB1CR		0x7f318000
 
 /* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02025080
 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 #define CONFIG_SYS_EBC_PB2CR		0x7f11a000
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000