X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=include%2Fmpc85xx.h;h=3753e47edfb5336ecd371028dea708b961854bc9;hb=e4a63a45e800c2413521f91bd8e8a1e2d8587c28;hp=a4f5c619d1412a978883638ef1078f6e1744533c;hpb=42d1f0394bef0624fc9664714d54bb137931d6a6;p=karo-tx-uboot.git

diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index a4f5c619d1..3753e47edf 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -1,32 +1,67 @@
 /*
+ * Copyright 2004, 2007 Freescale Semiconductor.
  * Copyright(c) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
  */
 
 #ifndef	__MPC85xx_H__
 #define __MPC85xx_H__
 
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
-
 #if defined(CONFIG_E500)
 #include <e500.h>
 #endif
 
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void);
-uint dma_check(void);
-int dma_xfer(void *dest, uint count, void *src);
-#endif
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control Register                                  9-8
+/*
+ * SCCR - System Clock Control Register, 9-8
  */
-#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable        */
-#define SCCR_DFBRG_MSK  0x00000003      /* Division factor of BRGCLK Mask */
+#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
+#define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
 #define SCCR_DFBRG_SHIFT 0
 
-#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4         */
-#define SCCR_DFBRG01    0x00000001      /* BRGCLK division by 16 (normal op.)*/
-#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64        */
-#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256       */
+#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
+#define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
+#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
+#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR 		CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW 	CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR 		CONFIG_SYS_CCSRBAR
+#endif
 
 #endif	/* __MPC85xx_H__ */