X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=include%2Fvirtex2.h;h=503df9abaeaa2cc9e2769ecb6c776393d356d9fc;hb=f029fa8f4eaf0c29d4e96ffe46cb91a4892b9fe0;hp=7b7825f513e358be83dbbbb753bd75569892d007;hpb=14cfc4f3735d9704cb6a630ef302be596d380684;p=karo-tx-uboot.git

diff --git a/include/virtex2.h b/include/virtex2.h
index 7b7825f513..503df9abae 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,8 +11,6 @@
 
 #include <xilinx.h>
 
-extern struct xilinx_fpga_op virtex2_op;
-
 /*
  * Slave SelectMap Implementation function table.
  */
@@ -40,12 +38,19 @@ typedef struct {
 	xilinx_wdata_fn	wdata;
 } xilinx_virtex2_slave_serial_fns;
 
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS	&virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS	NULL
+#endif
+
 /* Device Image Sizes (in bytes)
  *********************************************************************/
-#define XILINX_XC2V40_SIZE		(338208 / 8)
-#define XILINX_XC2V80_SIZE		(597408 / 8)
-#define XILINX_XC2V250_SIZE		(1591584 / 8)
-#define XILINX_XC2V500_SIZE		(2557857 / 8)
+#define XILINX_XC2V40_SIZE	(338208 / 8)
+#define XILINX_XC2V80_SIZE	(597408 / 8)
+#define XILINX_XC2V250_SIZE	(1591584 / 8)
+#define XILINX_XC2V500_SIZE	(2557857 / 8)
 #define XILINX_XC2V1000_SIZE	(3749408 / 8)
 #define XILINX_XC2V1500_SIZE	(5166240 / 8)
 #define XILINX_XC2V2000_SIZE	(6808352 / 8)
@@ -58,39 +63,51 @@ typedef struct {
 /* Descriptor Macros
  *********************************************************************/
 #define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
-{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #endif /* _VIRTEX2_H_ */