X-Git-Url: https://git.karo-electronics.de/?a=blobdiff_plain;f=packages%2Fhal%2Farm%2Fmx53%2Fkaro%2Fv1_0%2Finclude%2Fhal_platform_setup.h;h=34be254cbaee4e2c5f803dea57ffb19ab9468625;hb=7e93b1a0eb40192627d7402be3f6b5eaa7e607b4;hp=4b659414ab42d4b7290bfb3e9aa5b08bb6baff68;hpb=db033af023c85047e78d818c8cdb41ef41083229;p=karo-tx-redboot.git diff --git a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h index 4b659414..34be254c 100644 --- a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h +++ b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h @@ -42,23 +42,17 @@ //####ECOSGPLCOPYRIGHTEND#### //=========================================================================== -#include // System-wide configuration info -#include CYGBLD_HAL_VARIANT_H // Variant specific configuration -#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration -#include // Variant specific hardware definitions -#include // MMU definitions -#include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions +#include // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include // Variant specific hardware definitions +#include // MMU definitions +#include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions #include CYGHWR_MEMORY_LAYOUT_H #define CPU_CLK CYGNUM_HAL_ARM_TX53_CPU_CLK -#if defined(CYGNUM_HAL_ARM_TX53_DDR2_CLK) -#define SDRAM_CLK CYGNUM_HAL_ARM_TX53_DDR2_CLK -#elif defined(CYGNUM_HAL_ARM_TX53_DDR3_CLK) -#define SDRAM_CLK CYGNUM_HAL_ARM_TX53_DDR3_CLK -#else -#error SDRAM clock not defined -#endif +#define SDRAM_CLK 400 #define DEBUG_LED_BIT 20 #define LED_GPIO_BASE GPIO2_BASE_ADDR @@ -86,6 +80,14 @@ #define PLATFORM_PREAMBLE flash_header +#ifdef RAM_BANK1_SIZE +#define REDBOOT_RAM_START (RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET) +#else +#define REDBOOT_RAM_START (RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET) +#endif + +#define redboot_v2p(v) ((v) - __text_start + REDBOOT_RAM_START) + // This macro represents the initial startup code for the platform .macro _platform_setup1 KARO_TX53_SETUP_START: @@ -111,8 +113,6 @@ KARO_TX53_SETUP_START: orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB mcr p15, 0, r0, c1, c0, 0 - setup_sdram - /* ARM errata ID #468414 */ mrc 15, 0, r1, c1, c0, 1 orr r1, r1, #(1 << 5) /* enable L1NEON bit */ @@ -146,26 +146,27 @@ init_aips_start: str r9, [r10, #GPIO_GDIR] LED_INIT - LED_BLINK 1 init_clock_start: init_clock - LED_BLINK 2 + LED_BLINK #1 -Normal_Boot_Continue: /* * Note: * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity */ STACK_Setup: @ Set up a stack [for calling C code] - ldr r1, =__startup_stack - ldr r2, =RAM_BANK0_BASE - orr sp, r1, r2 + /* stack is always in the first memory bank, so there is no + * need to fixup the address + */ + ldr sp, .__startup_stack @ Create MMU tables + + LED_BLINK #2 bl hal_mmu_init - LED_BLINK 3 + LED_BLINK #3 /* Workaround for arm erratum #709718 */ @ Setup PRRR so device is always mapped to non-shared @@ -174,7 +175,11 @@ STACK_Setup: mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register @ Enable MMU - ldr r2, =10f + adr r2, mmu_switched +#ifdef RAM_BANK1_SIZE + ldr r1, =(__text_start - REDBOOT_RAM_START) + sub r2, r2, r1 +#endif mrc MMU_CP, 0, r1, MMU_Control, c0 orr r1, r1, #7 @ enable MMU bit orr r1, r1, #0x800 @ enable z bit @@ -187,9 +192,10 @@ STACK_Setup: mcr MMU_CP, 0, r1, MMU_Control, c0, 1 mov pc, r2 @ Change address spaces + .ltorg .align 5 -10: - LED_BLINK 4 +mmu_switched: + LED_BLINK #4 .endm @ _platform_setup1 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ @@ -199,7 +205,7 @@ STACK_Setup: * not forced to user-mode. */ ldr r0, =AIPS1_CTRL_BASE_ADDR - ldr r1, AIPS1_PARAM + ldr r1, =0x77777777 str r1, [r0, #0x00] str r1, [r0, #0x04] ldr r0, =AIPS2_CTRL_BASE_ADDR @@ -230,15 +236,17 @@ osc_ok: setup_pll PLL3_BASE_ADDR, 400 /* Switch peripherals to PLL3 */ - ldr r1, CCM_CBCMR_VAL1 + ldr r1, [r0, #CLKCTL_CBCMR] + bic r1, #(3 << 12) + orr r1, #(1 << 12) str r1, [r0, #CLKCTL_CBCMR] - ldr r1, CCM_CBCDR_VAL1 + ldr r1, [r0, #CLKCTL_CBCDR] + orr r1, r1, #(1 << 25) str r1, [r0, #CLKCTL_CBCDR] 1: /* make sure change is effective */ ldr r1, [r0, #CLKCTL_CDHIPR] - LED_BLINK 1 cmp r1, #0x0 bne 1b @@ -256,16 +264,18 @@ osc_ok: #error Bad SDRAM_CLK #endif /* Switch peripheral to PLL2 */ - ldr r1, CCM_CBCDR_VAL2 + ldr r1, [r0, #CLKCTL_CBCDR] + bic r1, #(1 << 25) str r1, [r0, #CLKCTL_CBCDR] - ldr r1, CCM_CBCMR_VAL2 + ldr r1, [r0, #CLKCTL_CBCMR] + bic r1, #(3 << 12) + orr r1, #(2 << 12) str r1, [r0, #CLKCTL_CBCMR] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] - LED_BLINK 1 cmp r1, #0x0 bne 1b @@ -289,8 +299,8 @@ osc_ok: ldr r1, W_CSCMR1_VAL str r1, [r0, #CLKCTL_CSCMR1] - mov r1, #0x00000 - str r1, [r0, #CLKCTL_CCDR] + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] /* for cko - for ARM div by 8 */ mov r1, #0x000A0000 @@ -326,27 +336,6 @@ end_clk_init: ands r1, r1, #0x1 beq 101b .endm - - .macro setup_sdram -#if 0 - /* Decrease the DRAM SDCLK pads to HIGH Drive strength */ - ldr r0, =IOMUXC_BASE_ADDR - ldr r1, =0x000000e5 - str r1, [r0, #0x4b8] - /* Change the delay line configuration */ - ldr r0, =ESDCTL_BASE_ADDR - ldr r1, =0x00f49400 - str r1, [r0, #ESDCTL_ESDCDLY1] - ldr r1, =0x00f49a00 - str r1, [r0, #ESDCTL_ESDCDLY2] - ldr r1, =0x00f49100 - str r1, [r0, #ESDCTL_ESDCDLY3] - ldr r1, =0x00f48900 - str r1, [r0, #ESDCTL_ESDCDLY4] - ldr r1, =0x00f49400 - str r1, [r0, #ESDCTL_ESDCDLY5] -#endif - .endm #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) #define PLATFORM_SETUP1 #endif @@ -356,7 +345,7 @@ end_clk_init: .macro DELAY,ms .endm #else -#define CYGHWR_LED_MACRO LED_BLINK \x +#define CYGHWR_LED_MACRO LED_BLINK #\x .macro DELAY,ms ldr r10, =\ms @@ -364,7 +353,7 @@ end_clk_init: .endm .macro LED_BLINK,val - ldr r8, =\val + mov r8, \val bl led_blink .endm #endif @@ -380,10 +369,6 @@ end_clk_init: ldr r9, [r10, #GPIO_GDIR] orr r9, r9, #(1 << DEBUG_LED_BIT) str r9, [r10, #GPIO_GDIR] - // iomux - ldr r10, =IOMUXC_BASE_ADDR - mov r9, #LED_MUX_MODE - str r9, [r10, #LED_MUX_OFFSET] .endm #ifdef CYGOPT_HAL_ARM_TX53_DEBUG @@ -407,7 +392,7 @@ delay: subs r10, r10, #1 movmi pc, lr - ldr r9, =(36000 / 10 / 10) + ldr r9, =(36000 / 10) 2: subs r9, r9, #1 bne 2b @@ -448,6 +433,7 @@ _KARO_CECFG_START: _KARO_CECFG_END: .endm + .ltorg .align 5 .ascii "KARO TX53 " __DATE__ " " __TIME__ .align @@ -458,20 +444,85 @@ _KARO_CECFG_END: (((l) >> 8) & 0x0000FF00) | \ (((l) >> 24) & 0x000000FF)) -#define MXC_DCD_ITEM(addr, val) \ - .word CPU_2_BE_32(addr) ; \ - .word CPU_2_BE_32(val) +/* +CCM register set 0x53FD4000 0x53FD7FFF +EIM register set 0x63FDA000 0x63FDAFFF +NANDFC register set 0xF7FF0000 0xF7FFFFFF +IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF +DPLLC1 register 0x63F80000 0x63F83FFF +DPLLC2 register 0x63F84000 0x63F87FFF +DPLLC3 register 0x63F88000 0x63F8BFFF +DPLLC4 register 0x63F8C000 0x63F8FFFF +ESD RAM controller register 0x63FD9000 0x63FD9FFF +M4IF register 0x63FD8000 0x63FD8FFF +DDR 0x70000000 0xEFFFFFFF +EIM 0xF0000000 0xF7FEFFFF +NANDFC Buffers 0xF7FF0000 0xF7FFFFFF +IRAM Free Space 0xF8006000 0xF8017FF0 +GPU Memory 0xF8020000 0xF805FFFF +*/ +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \ + ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \ + ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \ + ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \ + ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \ + ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \ + ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \ + ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \ + ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */) + + .macro mxc_dcd_item addr, val + .ifne CHECK_DCD_ADDR(\addr) + .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val) + .else + .error "Address \addr not accessible from DCD" + .endif + .endm + +#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_SZ_BYTE 1 #define MXC_DCD_CMD_SZ_SHORT 2 #define MXC_DCD_CMD_SZ_WORD 4 #define MXC_DCD_CMD_FLAG_WRITE 0x0 -#define MXC_DCD_CMD_FLAG_CLR 0x2 +#define MXC_DCD_CMD_FLAG_CLR 0x1 #define MXC_DCD_CMD_FLAG_SET 0x3 -#define MXC_DCD_CMD(type, flags, next) \ - .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) +#define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1)) +#define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1)) +#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1)) +#define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1)) + +#define MXC_DCD_START \ + .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \ +dcd_start: + + .macro MXC_DCD_END +1: + .ifgt . - dcd_start - 1768 + .error "DCD too large!" + .endif +dcd_end: + .endm + +#define MXC_DCD_CMD_WRT(type, flags) \ +1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type)) +#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ +1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \ + CPU_2_BE_32(addr), CPU_2_BE_32(mask) + +#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ +1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \ + CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) + +#define MXC_DCD_CMD_NOP() \ +1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) + + +#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) +#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) .macro CK_VAL, name, clks, offs, max .iflt \clks - \offs @@ -479,6 +530,8 @@ _KARO_CECFG_END: .else .ifle \clks - \offs - \max .set \name, \clks - \offs + .else + .error "Value \clks out of range for parameter \name" .endif .endif .endm @@ -499,175 +552,180 @@ _KARO_CECFG_END: .endif .endm -#define SDRAM_TYPE_DDR2 2 -#define SDRAM_TYPE_DDR3 3 - #define ESDMISC_DDR_TYPE_DDR3 0 #define ESDMISC_DDR_TYPE_LPDDR2 1 #define ESDMISC_DDR_TYPE_DDR2 2 -#define ESDOR_CLK_PERIOD 15625 /* base clock for ESDOR values 15.625uS */ - -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 -#define SDRAM_BURST_LENGTH 4 -#define BANK_ADDR_BITS 1 -#define COL_ADDR_BITS 10 -#define RALAT 4 -#define WALAT 0 -#define ADDR_MIRROR 0 -#define DDR_TYPE ESDMISC_DDR_TYPE_DDR2 - -#if SDRAM_SIZE > SZ_512M -#define ROW_ADDR_BITS 15 - -/* 1GiB SDRAM: MEM2G08D2DABG */ -/* ESDCFG0 0x0c */ -NS_VAL tRFC, 195, 1, 255 /* clks - 1 (0..255) */ -CK_VAL tXS, tRFC + 1 + NS_TO_CK(10), 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_VAL tXP, 2, 1, 7 /* clks - 1 (0..7) */ -CK_VAL tXPDLL /* => tXARD */, 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 35, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tCL, 5, 3, 8 /* clks - 3 (0..8) CAS Latency */ - -/* ESDCFG1 0x10 */ -NS_VAL tRCD, 13, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRP, 13, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRC, 58, 1, 31 /* clks - 1 (0..31) */ -NS_VAL tRAS, 45, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ -NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tMRD, 2, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tCWL, tCL + 3 - 1, 2, 6 /* clks - 2 (0..6) tCL - 1 */ - -/* ESDCFG2 0x14 */ -CK_VAL tDLLK, 200, 1, 511 /* clks - 1 (0..511) */ -NS_VAL tRTP, 8, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tWTR, 8, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRRD, 8, 1, 6 /* clks - 1 (0..6) */ -#else -#define ROW_ADDR_BITS 14 - -/* 512MiB SDRAM: V59C1G01(808) */ -/* ESDCFG0 0x0c */ -NS_VAL tRFC, 128, 1, 255 /* clks - 1 (0..255) */ -CK_VAL tXS, tRFC + 1 + NS_TO_CK(10), 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_VAL tXP, 2, 1, 7 /* clks - 1 (0..7) */ -CK_VAL tXPDLL, /* tXARD */ 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tCL, 5, 3, 8 /* clks - 3 (0..8) CAS Latency */ - -/* ESDCFG1 0x10 */ -NS_VAL tRCD, 15, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRP, 15, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRC, 60, 1, 31 /* clks - 1 (0..31) */ -NS_VAL tRAS, 45, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ -NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tMRD, 2, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tCWL, tCL + 3 - 1, 2, 6 /* clks - 2 (0..6) tCL - 1 */ +#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) -/* ESDCFG2 0x14 */ -CK_VAL tDLLK, 200, 1, 511 /* clks - 1 (0..511) */ -NS_VAL tRTP, 8, 1, 7 /* clks - 1 (0..7) */ -CK_VAL tWTR, 2, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRRD, 10, 1, 6 /* clks - 1 (0..6) */ -#endif +#define CKIL_FREQ_Hz 32768 +#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */ -/* ESDOR 0x30 */ -NS_VAL tXPR, 400, 1, 255 /* clks - 1 (1..255) */ - -#define tSDE_RST 0 /* not relevant for DDR2 */ -#define tRST_CKE ((200000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD) - -#define ESDSCR_MRS_VAL (0x8000 | (3 << 4) | \ - ((((tCL + 3) << 4) | \ - (tWR << 9) | \ - ((1 - (SDRAM_BURST_LENGTH / 8)) << 1)) << 16)) - -#elif CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR3 /* DDR3 SDRAM */ -#if SDRAM_SIZE > SZ_512M +#if SDRAM_SIZE > RAM_BANK0_SIZE #define BANK_ADDR_BITS 2 #else #define BANK_ADDR_BITS 1 #endif #define SDRAM_BURST_LENGTH 8 #define RALAT 5 -#define WALAT 1 +#define WALAT 0 +#define BI_ON 0 #define ADDR_MIRROR 0 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3 -/* 512/1024MiB SDRAM: NT5CB128M16P-CG */ +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ +#if SDRAM_CLK > 666 && SDRAM_CLK <= 800 +#define CL_VAL 11 +#define CWL_VAL 8 +#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666 +#define CL_VAL 9 // or 10 +#define CWL_VAL 7 +#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533 +#define CL_VAL 7 // or 8 +#define CWL_VAL 6 +#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400 +#define CL_VAL 6 +#define CWL_VAL 5 +#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333 +#define CL_VAL 5 +#define CWL_VAL 5 +#else +#error SDRAM clock out of range: 303 .. 800 +#endif + /* ESDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ -CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */ -CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ /* ESDCFG1 0x10 */ -NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */ -NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */ +CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ +CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ -NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */ +CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ -CK_VAL tCWL, 7, 2, 6 /* clks - 2 (0..6) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ /* ESDCFG2 0x14 */ CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ -CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ -CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ -CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ /* ESDOR 0x30 */ -CK_MAX tXPR, NS_TO_CK(160 + 10), 5, 1, 255 /* max(tRFC + 10, 5CK) */ - -#define tSDE_RST ((200000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD) -#define tRST_CKE ((500000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD) +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1) + /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to + * erroneous Erratum Engcm12377 + */ +#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1) + + +/* ESDOTC 0x08 */ +CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ +CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */ + +/* ESDPDC 0x04 */ +CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7 +CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 +CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 + +#define PRCT 0 +#define PWDT 5 +#define SLOW_PD 0 +#define BOTH_CS_PD 1 + +#define ESDPDC_VAL_0 ( \ + (PRCT << 28) | \ + (PRCT << 24) | \ + (tCKE << 16) | \ + (SLOW_PD << 7) | \ + (BOTH_CS_PD << 6) | \ + (tCKSRX << 3) | \ + (tCKSRE << 0) \ + ) + +#define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \ + (PWDT << 12) | \ + (PWDT << 8) \ + ) #define ROW_ADDR_BITS 14 #define COL_ADDR_BITS 10 +#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ +#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ +#define DLL_DISABLE 0 + .iflt tWR - 7 - .set ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \ - (((tWR - 3) << 9) | \ - (((tCL + 3) - 4) << 4)) << 16) + .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + ((tWR + 1 - 4) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) .else - .set ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \ - ((((tWR + 1) / 2) << 9) | \ - (((tCL + 3) - 4) << 4)) << 16) + .set mr0_val, ((1 << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + (((tWR + 1) / 2) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) .endif -#else -#error Unsupported SDRAM type selected -#endif - -#define ESDCFG0_VAL ( \ - ((tRFC) << 24) | \ - ((tXS) << 16) | \ - ((tXP) << 13) | \ - ((tXPDLL) << 9) | \ - ((tFAW) << 4) | \ - ((tCL) << 0)) \ - -#define ESDCFG1_VAL ( \ - ((tRCD) << 29) | \ - ((tRP) << 26) | \ - ((tRC) << 21) | \ - ((tRAS) << 16) | \ - ((tRPA) << 15) | \ - ((tWR) << 9) | \ - ((tMRD) << 5) | \ - ((tCWL) << 0)) \ - -#define ESDCFG2_VAL ( \ - ((tDLLK) << 16) | \ - ((tRTP) << 6) | \ - ((tWTR) << 3) | \ - ((tRRD) << 0)) +#define mr1_val ( \ + ((Rtt_Nom & 1) << 2) | \ + (((Rtt_Nom >> 1) & 1) << 6) | \ + (((Rtt_Nom >> 2) & 1) << 9) | \ + (DLL_DISABLE << 0) | \ + 0) +#define mr2_val ( \ + (Rtt_WR << 9) /* dynamic ODT */ | \ + (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \ + (1 << 6) | /* ASR: Automatic Self Refresh */\ + (((tCWL + 2) - 5) << 3) | \ + 0) +#define mr3_val 0 + +#define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ + (1 << 15) /* CON_REQ */ | \ + 0x80 | \ + (3 << 4) /* MRS command */ | \ + ((cs) << 3) | \ + ((mr) << 0) | \ + 0) + +#define ESDCFG0_VAL ( \ + (tRFC << 24) | \ + (tXS << 16) | \ + (tXP << 13) | \ + (tXPDLL << 9) | \ + (tFAW << 4) | \ + (tCL << 0)) \ + +#define ESDCFG1_VAL ( \ + (tRCD << 29) | \ + (tRP << 26) | \ + (tRC << 21) | \ + (tRAS << 16) | \ + (tRPA << 15) | \ + (tWR << 9) | \ + (tMRD << 5) | \ + (tCWL << 0)) \ + +#define ESDCFG2_VAL ( \ + (tDLLK << 16) | \ + (tRTP << 6) | \ + (tWTR << 3) | \ + (tRRD << 0)) #define BL (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ @@ -685,6 +743,13 @@ CK_MAX tXPR, NS_TO_CK(160 + 10), 5, 1, 255 /* max(tRFC + 10, 5CK) */ #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) +#define ESDOTC_VAL ((tAOFPD << 27) | \ + (tAONPD << 24) | \ + (tANPD << 20) | \ + (tAXPD << 16) | \ + (tODTLon << 12) | \ + (tODTLoff << 4)) + .macro flash_header __text_start: fcb_start: @@ -702,113 +767,39 @@ fcb_start: .word 0 /* BI Swap disabled */ .word 0 /* Bad Block marker offset in spare area */ fcb_end: -#if 1 - .word 0 -tRFC_VAL: - .byte tRFC -tXS_VAL: - .byte tXS -tXP_VAL: - .byte tXP -tXPDLL_VAL: - .byte tXPDLL -tFAW_VAL: - .byte tFAW -tCL_VAL: - .byte tCL -tRCD_VAL: - .byte tRCD -tRP_VAL: - .byte tRP -tRC_VAL: - .byte tRC -tRAS_VAL: - .byte tRAS -tRPA_VAL: - .byte tRPA -tWR_VAL: - .byte tWR -tMRD_VAL: - .byte tMRD -tCWL_VAL: - .byte tCWL -tDLLK_VAL: - .byte tDLLK -tRTP_VAL: - .byte tRTP -tWTR_VAL: - .byte tWTR -tRRD_VAL: - .byte tRRD -tXPR_VAL: - .byte tXPR -tSDE_RST_VAL: - .byte tSDE_RST -tRST_CKE_VAL: - .byte tRST_CKE - .align 2 -W_ESDCTL_VAL: - .word ESDCTL_VAL -W_ESDMISC_VAL: - .word ESDMISC_VAL -W_ESDCFG0_VAL: - .word ESDCFG0_VAL -W_ESDCFG1_VAL: - .word ESDCFG1_VAL -W_ESDCFG2_VAL: - .word ESDCFG2_VAL -W_ESDOR_VAL: - .word ESDOR_VAL -W_ESDSCR_MRS_VAL: - .word ESDSCR_MRS_VAL -#endif -#if 0 -#undef ESDCFG0_VAL -#undef ESDCFG1_VAL -#undef ESDMISC_VAL - -#define ESDCFG0_VAL 0x9f5152e3 -#define ESDCFG1_VAL 0xb68e8a63 -#define ESDMISC_VAL 0x00011740 -W_ESDMISC_VAL_FSL: - .word ESDMISC_VAL -W_ESDCFG0_VAL_FSL: - .word ESDCFG0_VAL -W_ESDCFG1_VAL_FSL: - .word ESDCFG1_VAL -#endif + .org 0x400 ivt_header: .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) app_start_addr: - .long reset_vector + .long redboot_v2p(reset_vector) .long 0x0 dcd_ptr: - .long dcd_hdr + .long redboot_v2p(dcd_hdr) boot_data_ptr: - .word boot_data + .word redboot_v2p(boot_data) self_ptr: - .word ivt_header + .word redboot_v2p(ivt_header) app_code_csf: .word 0x0 .word 0x0 boot_data: - .long __text_start + .long redboot_v2p(__text_start) image_len: .long REDBOOT_IMAGE_SIZE plugin: .word 0 ivt_end: - #define DCD_VERSION 0x40 dcd_hdr: - .word CPU_2_BE_32((0xd2 << 24) | - ((dcd_end - .) << 8) | DCD_VERSION) -dcd_start: - MXC_DCD_CMD(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end) + MXC_DCD_START + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + + MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V + /* disable all irrelevant clocks */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc00cf) + MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff) MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3) MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000) MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x00000000) @@ -818,176 +809,155 @@ dcd_start: MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000) MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000) - MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x174, 0x00000011) /* EIM_D18 => GPIO2[20] STK5-LED */ + MXC_DCD_ITEM(IOMUXC_BASE_ADDR + LED_MUX_OFFSET, LED_MUX_MODE) /* EIM_D18 => GPIO2[20] STK5-LED */ + MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x318, 0x11) /* GPIO_1 => LCD Backlight */ MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */ -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 - /* setup SDRAM pads */ - MXC_DCD_ITEM(0x53fa8554, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - MXC_DCD_ITEM(0x53fa8560, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - MXC_DCD_ITEM(0x53fa8594, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - MXC_DCD_ITEM(0x53fa8584, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - - MXC_DCD_ITEM(0x53fa8558, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - MXC_DCD_ITEM(0x53fa8568, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - MXC_DCD_ITEM(0x53fa8590, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - MXC_DCD_ITEM(0x53fa857c, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - - MXC_DCD_ITEM(0x53fa8564, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 - MXC_DCD_ITEM(0x53fa8580, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 - MXC_DCD_ITEM(0x53fa8570, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - MXC_DCD_ITEM(0x53fa8578, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - - MXC_DCD_ITEM(0x53fa872c, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B3DS - MXC_DCD_ITEM(0x53fa8728, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B2DS - MXC_DCD_ITEM(0x53fa871c, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B1DS - MXC_DCD_ITEM(0x53fa8718, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B0DS - - MXC_DCD_ITEM(0x53fa8574, 0x00280000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - MXC_DCD_ITEM(0x53fa8588, 0x00280000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - MXC_DCD_ITEM(0x53fa86f0, 0x00280000) @ IOMUXC_SW_PAD_CTL_GRP_ADDDS - MXC_DCD_ITEM(0x53fa8720, 0x00280000) @ IOMUXC_SW_PAD_CTL_GRP_CTLDS - - MXC_DCD_ITEM(0x53fa86fc, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRPKE - -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 - MXC_DCD_ITEM(0x53fa86f4, 0x00000200) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DQS DIFF mode - MXC_DCD_ITEM(0x53fa8714, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Data CMOS mode - MXC_DCD_ITEM(0x53fa8724, 0x06000000) @ IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=01 +#if SDRAM_CLK > 333 + MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */ #else - MXC_DCD_ITEM(0x53fa86f4, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DQS DIFF mode - MXC_DCD_ITEM(0x53fa8714, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Data CMOS mode - MXC_DCD_ITEM(0x53fa8724, 0x04000000) @ IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=10 + MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */ #endif - /* memory timing setup */ - MXC_DCD_ITEM(0x63fd9088, 0x36353b38) - MXC_DCD_ITEM(0x63fd9090, 0x49434942) - MXC_DCD_ITEM(0x63fd90F8, 0x00000800) - MXC_DCD_ITEM(0x63fd907c, 0x01350138) - MXC_DCD_ITEM(0x63fd9080, 0x01380139) - MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL) @ ESDMISC + MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */ + +#define DDR_SEL_VAL 0 +#define DSE_VAL 5 +#define ODT_VAL 2 + +#define DDR_SEL_SHIFT 25 +#define ODT_SHIFT 22 +#define DSE_SHIFT 19 +#define DDR_INPUT_SHIFT 9 +#define HYS_SHIFT 8 +#define PKE_SHIFT 7 +#define PUE_SHIFT 6 +#define PUS_SHIFT 4 + +#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) +#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define ODT_MASK (ODT_VAL << ODT_SHIFT) + +#define DQM_VAL DSE_MASK +#define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT)) +#define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_VAL DSE_MASK +#define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) + + MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */ + MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */ + MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */ + MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */ + MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */ + MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */ + + MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */ + MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */ + MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */ + MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */ + + MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */ + MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */ + MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */ + MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */ + + MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */ + MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */ + + MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */ + MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */ + + MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */ + MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */ + + MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */ + MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */ + + MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */ + MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */ + MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */ + MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */ + MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */ + MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */ + + /* calibration defaults */ + MXC_DCD_ITEM(0x63fd904c, 0x001f001f) + MXC_DCD_ITEM(0x63fd9050, 0x001f001f) + MXC_DCD_ITEM(0x63fd907c, 0x011e011e) + MXC_DCD_ITEM(0x63fd9080, 0x011f0120) + MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b) + MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f) + + MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL) MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL) MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL) MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL) MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL) - MXC_DCD_ITEM(0x63fd902c, 0x000026d2) @ command delay - MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL) @ out of reset delays - MXC_DCD_ITEM(0x63fd9008, 0x12273030) @ ODT timings - MXC_DCD_ITEM(0x63fd9004, 0x00030012) @ Power down control - - /********************************* - * DDR device configuration: - **********************************/ - /* CS0 */ -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 - MXC_DCD_ITEM(0x63fd901c, 0x04008010) - MXC_DCD_ITEM(0x63fd901c, 0x00008020) - MXC_DCD_ITEM(0x63fd901c, 0x00008020) -#endif - MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL) - //MXC_DCD_ITEM(0x63fd901c, 0x0a528030) @ MRS: BL: 4, BT: seq, CL: 5, WR: 6 -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 - MXC_DCD_ITEM(0x63fd901c, 0x03868031) @ EMRS(1): OCD calibration default - MXC_DCD_ITEM(0x63fd901c, 0x00068031) @ EMRS(1): OCD calibration exit - MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ EMRS(2): 0 -#else - MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ MR2: 0 - MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ MR3: 0 - MXC_DCD_ITEM(0x63fd901c, 0x00028031) @ MR1: - MXC_DCD_ITEM(0x63fd901c, 0x092080b0) @ MR0: WHY 80b0 instead of 8030? Undocumented bit# 7? - MXC_DCD_ITEM(0x63fd901c, 0x04008040) -#endif -#if BANK_ADDR_BITS > 1 -#if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2 - MXC_DCD_ITEM(0x63fd901c, 0x04008018) - MXC_DCD_ITEM(0x63fd901c, 0x00008028) - MXC_DCD_ITEM(0x63fd901c, 0x00008028) -#endif - MXC_DCD_ITEM(0x63fd901c, 0x0a528038) @ MRS: BL: 4, BT: seq, CL: 5, WR: 6 - MXC_DCD_ITEM(0x63fd901c, 0x03868039) @ EMRS(1): OCD calibration default - MXC_DCD_ITEM(0x63fd901c, 0x00068039) @ EMRS(1): OCD calibration exit - MXC_DCD_ITEM(0x63fd901c, 0x0000803a) @ EMRS(2): 0 -#endif - MXC_DCD_ITEM(0x63fd9020, 0x00005800) - MXC_DCD_ITEM(0x63fd9058, 0x00033332) @ ODT control: 50Ohms, ODT act enable - MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd902c, 0x000026d2) + MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL) + MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL) + MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0) - MXC_DCD_ITEM(0x63fd901c, 0x00448031) @ full drive strength, enable 50ohm ODT - MXC_DCD_ITEM(0x63fd901c, 0x04008018) - MXC_DCD_ITEM(0x63fd901c, 0x00000000) + /* MR0..3 - CS0 */ + MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - /* Enable ZQ calibration to tightly control the impedance of the DDR IO pads */ - MXC_DCD_ITEM(0x63fd9040, 0x04b80003) @ keep ZQ HW control values and enable it -#else -MXC_DCD_ITEM(0x53fa8554, 0x00300000) -MXC_DCD_ITEM(0x53fa8560, 0x00300000) -MXC_DCD_ITEM(0x53fa8594, 0x00300000) -MXC_DCD_ITEM(0x53fa8584, 0x00300000) - -MXC_DCD_ITEM(0x53fa8558, 0x00f00000) -MXC_DCD_ITEM(0x53fa8568, 0x00f00000) -MXC_DCD_ITEM(0x53fa8590, 0x00f00000) -MXC_DCD_ITEM(0x53fa857c, 0x00f00000) - -MXC_DCD_ITEM(0x53fa8564, 0x00300040) -MXC_DCD_ITEM(0x53fa8580, 0x00300040) -MXC_DCD_ITEM(0x53fa8570, 0x00300000) -MXC_DCD_ITEM(0x53fa8578, 0x00300000) - -MXC_DCD_ITEM(0x53fa872c, 0x00300000) -MXC_DCD_ITEM(0x53fa8728, 0x00300000) -MXC_DCD_ITEM(0x53fa871c, 0x00300000) -MXC_DCD_ITEM(0x53fa8718, 0x00300000) - -MXC_DCD_ITEM(0x53fa8574, 0x00300000) -MXC_DCD_ITEM(0x53fa8588, 0x00300000) -MXC_DCD_ITEM(0x53fa86f0, 0x00300000) -MXC_DCD_ITEM(0x53fa8720, 0x00300000) - -MXC_DCD_ITEM(0x53fa86fc, 0x00000000) - -MXC_DCD_ITEM(0x53fa86f4, 0x00000000) -MXC_DCD_ITEM(0x53fa8714, 0x00000000) - -MXC_DCD_ITEM(0x53fa8724, 0x04000000) - -MXC_DCD_ITEM(0x63fd9088, 0x35343535) -MXC_DCD_ITEM(0x63fd9090, 0x4d444c44) -MXC_DCD_ITEM(0x63fd907c, 0x01370138) -MXC_DCD_ITEM(0x63fd9080, 0x013b013c) - -MXC_DCD_ITEM(0x63fd9018, 0x00011740) -MXC_DCD_ITEM(0x63fd9000, 0xc3190000) -MXC_DCD_ITEM(0x63fd900c, 0x9f5152e3) -MXC_DCD_ITEM(0x63fd9010, 0xb68e8a63) -MXC_DCD_ITEM(0x63fd9014, 0x01ff00db) - -MXC_DCD_ITEM(0x63fd902c, 0x000026d2) -MXC_DCD_ITEM(0x63fd9030, 0x009f0e21) -MXC_DCD_ITEM(0x63fd9008, 0x12273030) -MXC_DCD_ITEM(0x63fd9004, 0x0002002d) -@ MR0 - CS0 -MXC_DCD_ITEM(0x63fd901c, 0x00008032) -MXC_DCD_ITEM(0x63fd901c, 0x00008033) -MXC_DCD_ITEM(0x63fd901c, 0x00028031) -MXC_DCD_ITEM(0x63fd901c, 0x092080b0) -MXC_DCD_ITEM(0x63fd901c, 0x04008040) -@ MR0 - CS1 -#if SDRAM_SIZE > SZ_512M -MXC_DCD_ITEM(0x63fd901c, 0x0000803a) -MXC_DCD_ITEM(0x63fd901c, 0x0000803b) -MXC_DCD_ITEM(0x63fd901c, 0x00028039) -MXC_DCD_ITEM(0x63fd901c, 0x09208138) - -MXC_DCD_ITEM(0x63fd901c, 0x04008048) -#endif -MXC_DCD_ITEM(0x63fd9020, 0x00005800) -MXC_DCD_ITEM(0x63fd9040, 0x04b80003) -MXC_DCD_ITEM(0x63fd9058, 0x00022227) -MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */ +#if BANK_ADDR_BITS > 1 + /* MR0..3 - CS1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */ #endif - MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V + MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */ + MXC_DCD_ITEM(0x63fd9058, 0x00022222) + + MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */ + + /* ZQ calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */ + MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + + /* DQS calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */ + + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + + /* WR DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x00008000) + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a4, 0x00000010) + + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + + /* RD DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a0, 0x00000010) + + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */ + MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1) + + /* DDR calibration done */ + MXC_DCD_ITEM(0x63fd901c, 0x00000000) /* setup NFC pads */ /* MUX_SEL */ @@ -1022,24 +992,9 @@ MXC_DCD_ITEM(0x63fd901c, 0x00000000) MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0 -dcd_end: + MXC_DCD_END .endm -AIPS1_PARAM: .word 0x77777777 -MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET - -#if SDRAM_CLK > 333 -CCM_CBCDR_VAL1: .word 0x02888944 -CCM_CBCMR_VAL1: .word 0x00015154 -CCM_CBCDR_VAL2: .word 0x00888944 -CCM_CBCMR_VAL2: .word 0x00016154 -#else -CCM_CBCDR_VAL1: .word 0x02888644 -CCM_CBCMR_VAL1: .word 0x00015154 -CCM_CBCDR_VAL2: .word 0x00888644 -CCM_CBCMR_VAL2: .word 0x00016154 -#endif - W_CSCMR1_VAL: .word 0xa6a2a020 W_CSCDR1_VAL: .word 0x00080b18 W_DP_OP_1000: .word DP_OP_1000