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(parent: f6c9ce6) | patch
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
authorBryan Brinsko <bryan.brinsko@rockwellcollins.com>
Tue, 24 Mar 2015 16:25:12 +0000 (11:25 -0500)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 8 Sep 2015 19:47:21 +0000 (21:47 +0200)
commitde925a605ef6fcb372802b3e3814f778cd82fe43
treef7e8ffdeea75a5d847705f2e18fff81904d7e9fatree | snapshot
parentf6c9ce63e54787d26adc3ea18d1ad07f80202301commit | diff
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
arch/arm/include/asm/system.h diff | blob | history
arch/arm/lib/cache-cp15.c diff | blob | history
UBoot for KaRo TX COM modules