ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.

ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.

The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.

With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>