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(parent: 4cb0add) | patch
drm/radeon: enable mgcg on SI
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 14 Aug 2013 22:53:56 +0000 (18:53 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:52 +0000 (16:30 -0400)
commit090f4b6ad38eec0c24dcdc9d01cc22077c3b9d22
treed87ce068b466586c4defad81c870483f29aa9f1atree | snapshot
parent4cb0add259179ca8634fc0fddb2274534a58ff2dcommit | diff
drm/radeon: enable mgcg on SI

Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_asic.c diff | blob | history
Beck SC1x5 Kernel