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ASoC: fsl_esai: Only bypass sck_div for EXTAL source
authorNicolin Chen <Guangyu.Chen@freescale.com>
Tue, 6 May 2014 08:56:00 +0000 (16:56 +0800)
committerNitin Garg <nitin.garg@freescale.com>
Fri, 16 Jan 2015 03:16:50 +0000 (21:16 -0600)
commit0a4d5f8a7ef5823d44e9c5bf70be309316b0022c
tree6bc48b2b88f6ac490b95c6f64b25120b2b321fe9tree | snapshot
parent7a9a12bd9e17fc0222a949c1443db9bc6a436fd0commit | diff
ASoC: fsl_esai: Only bypass sck_div for EXTAL source

ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.

So this patch adds an extra check in the code.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1)
sound/soc/fsl/fsl_esai.c diff | blob | history
Linux kernel for KaRo TX COM modules