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ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionality
authorJason Liu <r64343@freescale.com>
Mon, 14 May 2012 13:41:05 +0000 (21:41 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:36 +0000 (08:34 +0200)
commit0dff68cc20e29feca8f611a231ef90ef325ff9a3
tree4e76224718887694176af4774b61014d2eb153c4tree | snapshot
parentc3cf4331cf4cf70256f55f936af8f41f551d97c9commit | diff
ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionality

L2 cache can be configured to serve as OCRAM.  This patch adds
code to check this configuration, and reset it to L2 cache function
before enabling the L2 cache.

Signed-off-by: Jason Liu <r64343@freescale.com>
arch/arm/mach-mx6/mm.c diff | blob | history
Linux kernel for KaRo TX COM modules