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(parent: 0ef9db6) | patch
clk: tegra: Add Super Gen5 Logic
authorBill Huang <bilhuang@nvidia.com>
Thu, 18 Jun 2015 21:28:35 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Thu, 17 Dec 2015 12:37:55 +0000 (13:37 +0100)
commit139fd30943c3c8ed76d0ce08ff711cfff3b118ec
treee5d3d9bec2145062c1ad25c44f50d21ab95737bbtree | snapshot
parent0ef9db6cf24dbb58118818e64198d9a030e4697ecommit | diff
clk: tegra: Add Super Gen5 Logic

Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-super-gen4.c diff | blob | history
drivers/clk/tegra/clk.h diff | blob | history
Beck SC1x5 Kernel